Texas Instruments Evaluation Module for TPS2554 TPS2554EVM-010 TPS2554EVM-010 데이터 시트
제품 코드
TPS2554EVM-010
V
IN
Oscilloscope
-
+
TPS2554EVM-010
J2
D1
J1
TP5
7" Twisted Pair, #20AWG
-
+
TP2
EVM Assembly Drawings and Layout Guidelines
Figure 2. Typical TPS2554/5EVM Test Setup
4
EVM Assembly Drawings and Layout Guidelines
4.1
Layout Guidelines
•
TPS2554/55 placement: Place the TPS2554/55 near the USB output connector and the 150-
µ
F OUT
pin filter capacitor. Connect the exposed pad to the GND pin and the system ground plane using a via
array.
array.
•
IN pin bypass capacitance: Place the 100-nF bypass capacitor near the IN and GND pins, and make
the connection using a low-inductance trace.
the connection using a low-inductance trace.
•
ILIM0 and ILIM1 pin connections: Current-limit accuracy can be compromised by stray current
leakage from a higher voltage source to the ILIM0 or ILIM1 pins. Ensure that adequate spacing exists
between IN pin copper/trace and ILIM0 pin trace to prevent contaminate buildup during the PCB
assembly process. If a low-current-limit setpoint is required (R
leakage from a higher voltage source to the ILIM0 or ILIM1 pins. Ensure that adequate spacing exists
between IN pin copper/trace and ILIM0 pin trace to prevent contaminate buildup during the PCB
assembly process. If a low-current-limit setpoint is required (R
ILIMx
>
200 k
Ω
), use ILIM1 for this case,
as it is further away from the IN pin.
4.2
PCB Drawings
The
through
show component placement and layout of the EVM.
5
SLVU462
–
June 2011
TPS2554 and TPS2555 Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated