Texas Instruments TLK100 Internal LDO's EVM TLK100INTEVM TLK100INTEVM 데이터 시트

제품 코드

TLK100INTEVM

TLK100INTEVM Specification

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2.1

Usage Setup and Configuration

Power for the TLK100INTEVM is supplied via MIl connector.

•

If 5V is supplied, the on-board U100 voltage regulator converts the 5V to 3.3V for the device. J100
should be removed.

•

If 3.3V is supplied from the MIl connector, J100 needs to be on; R101 should be assembled and R102
should be removed.

2.2

Address Settings

The PMD address for TLK100INTEVM Physical Layer device is set by the following jumpers:

J107: PHY ID [0]
J106: PHY ID [1]
J105: PHY ID [2]

•

Default board setting for the PHY Address is 01 h

•

The board may be set to PHY Address 00h-07h by adding jumper J105-J107.

2.3

TLK100INTEVM Connections

The following table describes the connections of the TLK100INTEVM:

Table 1. TLK100INTEVM Connections

Jumper

Name

Function

P100

MII Male Connector

MII interface

J100

MII 3V3 option

Use 3V3 MII supply

J102

RESET N

Reset the device

J108

Central Tap voltage selector

Use 3.3V/1.8V central tap voltage

U105

RJ45

RJ45 Ethernet connector

J105-J107(Not populated)

PHY ID[0:2]

Config PHY ID address

J103

25M out

25M clock output

J101

MDI_EN

Disable auto crossover and enable.

TLK100INTEVM Specification

3.1

Overview

The TLK100INTEVM is a Texas Instruments platform that allows evaluation of the TLK100 device; and, it
demonstrates the advanced features specified in the TLK100 data sheet. The EVM supports 10/100
Base-T and is compliant with IEEE 802.3 standard.

The TLK100INTEVM works with a single supply (5V or 3.3V) from the MII. All other voltages required for
the TLK100 are internally generated in the device.

The TLK100INTEVM is designed to work in industrial temperatures.

3.2

Required Resources

Any equipment that provides a standard IEEE 802.3, Clause 22 MII DTE interface; e.g. SmartBits/Netcom
box.

TLK100 Internal Voltages EVM

SLLU118 – September 2009

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