Texas Instruments Test System for BQ27000 BQ27200 Based Circuit Boards BQ27X00-TESTER BQ27X00-TESTER 데이터 시트
제품 코드
BQ27X00-TESTER
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Cycle Count Since Learning Cycle Registers (CYCLL/CYCLH) — Address 0x28/0x29
Cycle Count Total Registers (CYCTL/CYCTH) — Address 0x2A/0x2B
Compensated State-of-Charge (CSOC) — Address 0x2C
Reserved Registers
EEPROM Enable Register (EE_EN) — Address 0x6E
EEPROM Data Registers (EE_DATA) — Address 0x76 — 0x7F
Initial Last Measured Discharge High Byte (ILMD) — Address 0x76
SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
CYCL is the cycle count since the last learning cycle. Each count indicates an increment of CYCT since there
was a learning cycle. This register is cleared every time there is a learning cycle. When this count reaches 32, it
forces the CI flag in FLAGS to a 1. The host system has read-only access to this register pair.
was a learning cycle. This register is cleared every time there is a learning cycle. When this count reaches 32, it
forces the CI flag in FLAGS to a 1. The host system has read-only access to this register pair.
CYCT is the cycle count since a full reset. A full reset clears this register. Each count indicates a cumulative
discharge equal to the Design Capacity (256 * ILMD). The host system has read-only access to this register pair.
discharge equal to the Design Capacity (256 * ILMD). The host system has read-only access to this register pair.
CSOC reports the compensated available capacity as a percentage of the last measured discharge value (LMD).
The equation is:
The equation is:
CSOC (%) = 100 * CACT/LMD
The host system has read-only access to this register.
Addresses 0x2D — 0x6D and Address 0x6F — 0x75 are reserved and cannot be written by host.
This register is used to enable host writes to EEPROM data locations (addresses 0x76 — 0x7F). The host must
write data 0xDD to this register to enable EEPROM programming. See the Programming the EEPROM section
for further information on programming the EEPROM bytes. Care should be taken to insure that no value except
0xDD is written to this location.
write data 0xDD to this register to enable EEPROM programming. See the Programming the EEPROM section
for further information on programming the EEPROM bytes. Care should be taken to insure that no value except
0xDD is written to this location.
The EEPROM data registers contain information vital to the performance of the device. These registers are to be
programmed during pack manufacturing to allow flexibility in the design values of the battery to be monitored.
The EEPROM data registers are listed in
programmed during pack manufacturing to allow flexibility in the design values of the battery to be monitored.
The EEPROM data registers are listed in
. Detailed descriptions of what should be programmed follow.
See the Programming the EEPROM section for detailed information on writing the values to EEPROM.
Table 2. bq27000/bq27200 EEPROM Memory Map
Address
Name
Function
0x7F
TCOMP
Temperature compensation constants, OR, ID#1
0x7E
DCOMP
Discharge rate compensation constants, OR, ID#2
0x7D
IMLC
Initial max load current, OR, ID#3
0x7C
PKCFG
Pack configuration values
0x7B
TAPER
Aging estimate enable [7], charge termination taper current [6:0]
0x7A
DMFSD
Digital magnitude filter and self-discharge rate constants
0x79
ISLC
Initial standby load current
0x78
SEDV1
Scaled EDV1 threshold
0x77
SEDVF
Scaled EDVF threshold
0x76
ILMD
Initial last measured discharge high byte
This register contains the scaled design capacity of the battery to be monitored. The equation to calculate the
initial LMD is:
initial LMD is:
ILMD = Design Capacity(mAh) * R
S
(m
Ω
) / (256*3.57)
where R
S
is the value of the sense resistor used in the system. This value is used to initialize the high byte of
LMD. The initial low byte value of LMD is 0.
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