Texas Instruments TPS65820 Evaluation Module TPS65820EVM TPS65820EVM 데이터 시트
제품 코드
TPS65820EVM
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT0
LSB
ACKNOWLEDGE
(hA or bqA
)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT 0
LSB
NOT
ACKNOWLEDGE
(hN or bqN)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
SCL
SDA
DATA LINE
STABLE
DATA
CHANGE
ALLOWED
BIT 5-1
I
2
C Read and Write Operations
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SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 2. I
2
C Naming Conventions Used
CONDITION
CODE
START sent from host
S
STOP sent from host
P
TPS65820 I
2
C slave address sent from host, bus direction set from host to TPS65820 (WRITE)
hA0
TPS65820 register address sent from TPS65820, bus direction is from TPS65820 to host (READ)
hA1
Non-valid I
2
C slave address sent from host
hA_N
Valid TPS65820 register address sent from host
HCMD
Non-valid TPS65820 register address sent from host
HCMD_N
I/O data byte (8 bits) sent from host to TPS65820
hDATA
I/O data byte (8 bits) sent from TPS65820 to host
bqDATA
Acknowledge (ACK) from host
hA
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS65820
bqA
Not acknowledge (NACK) from TPS65820
bqN
Figure 24. I
2
C operation waveforms
For normal data transfers, SDA is allowed to change only when SCL is low, and one clock pulse is used per bit
of data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high are
reserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition and
terminated with a stop condition.
of data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high are
reserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition and
terminated with a stop condition.
When addressed, the TPS65820 device generates an acknowledge bit after the reception of each byte by pulling
the SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is associated
with the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65820 leaves the data line high,
enabling a STOP condition generation.
the SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is associated
with the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65820 leaves the data line high,
enabling a STOP condition generation.
The TPS65820 supports the standard I
2
C one-byte write. The basic I
2
C read protocol has the following steps:
•
Host sends a start and sets TPS65820 I
2
C slave address in write mode
•
TPS65820 ACKs that this is a valid I
2
C address and that the bus is configured for write
•
Host sends TPS65820 register address
•
TPS65820 ACKs that this is a valid register and stores the register address to be read
•
Host sends a repeated start and TPS65820 I
2
C slave address, reconfiguring the bus for read
•
TPS65820 ACKs that this is a valid address and that bus is reconfigured
•
Bus is in read mode, TPS65820 starts sending data from selected register
Copyright © 2006–2008, Texas Instruments Incorporated
27
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