Texas Instruments TPS65820 Evaluation Module TPS65820EVM TPS65820EVM 데이터 시트
제품 코드
TPS65820EVM
ADC State Machine
LOAD ADC
CONFIGURATION
DATA FROM I 2C
TRIGGER MODE,
TRIGGER DELAY
TRIGGER DELAY
SAMPLE WAIT TIME,
HOLDOFF MODE
REPEAT ON/OFF
REPEAT ON/OFF
ALU MODE : AVG /MAX/MIN
NUMBER OF SAMPLES
ADC INPUT RANGE
ADC CHANNEL
ADC
ENABLED
(I2C) ?
TRIGGER
EDGE
DETECT
EXTERNAL
TRIGGER
HOLDOFF
ON
1) SET ADC
BUSY STATUS
2) START
CONVERSION
TRIGGER
EDGE
MODE
MODE
TRIGGER
HI
TRIGGER
LO
N
CONVERSIONS
?
N
TH
CONVERSION
DONE
WAIT TIME
0 µs to 20.5 msec
START TRIGGER
DELAY
1) LOAD DATA IN
ALU
2) ALU OUTPUT
STORED IN
ACCUMULATOR
ALU
DATA OUT OF
RANGE
REPEAT
MODE
1) LOAD I2C DATA
REGISTER WITH
ALU DATA
ALU DATA
2) SET ADC STATUS
TO DONE
3) INT SENT TO HOST
IF NON-MASKED
1) SET ADC_HI OR
ADC_LO FAULT
2) SET ADC STATUS
TO DONE
3) INT SENT TO HOST
IF NON-MASKED
CURRENT
CYCLE ENDS
HOST STARTS NEW
CONVERSION
CYCLE BY SETTING
ADC_EN=HI
YES
NO
YES
YES
YES, CHECK
TRIGGER
NO
NO
NO
NO
NO
NO, SEND
DATA
TO I2C
YES FAULT
DETECTED
DETECTED
YES
NO
FALLING
EDGE
RISING
EDGE
ADC CONVERSION
COMPLETE
ALU OUTPUT
DATA READY
DATA READY
YES
TRIGGER
VALID
TRIGGER
DELAY
OVER
NO, OPPOSITE
TRIGGER EDGE
HAPPENED
BEFORE DELAY
TIME
NO
YES
ADC
ENABLED
(I2C) ?
NO
YES
NO, SEND
DATA
TO I2C
ADC
ENABLED
(I2C) ?
NO, HOST ENDS
CURRENT
CONVERSION
CYCLE SETTING
ADC_EN=LO
YES, CURRENT
CONVERSION
CYCLE STILL
ACTIVE,
ADC_EN = HI
TPS
65800 READY
FOR NEW
CONVERSION
CYCLE
I2C WRITE OPERATION
CONFIGURES NEXT
CONVERSION CYCLE
ADC_EN=LO
NO,
ADC+EN=LO,
NEED TO
RECONFIGURE
ADC
PARAMETERS
ALU
RESET
BATTERY DETECTION CIRCUIT
www.ti.com
..............................................................................................................................................................
SLVS663B – MAY 2006 – REVISED APRIL 2008
The ADC state machine with all the trigger and operation modes is shown in
Figure 52. Trigger and Operation Modes for the ADC State Machine
The ANLG1 pin has an internal current source connected between OUT and ANLG1, which is automatically
turned on when the OUT pin voltage exceeds the minimum system voltage set by the SYS_IN pin external
resistive divider. The current levels for ANLG1 pin can be programmed via I
turned on when the OUT pin voltage exceeds the minimum system voltage set by the SYS_IN pin external
resistive divider. The current levels for ANLG1 pin can be programmed via I
2
C register ADC_WAIT, bits
BATID_n. An integrated switch discharges the BAT pin to AGND1 when V(ANLG1)> V(OUT) – V
(NOBATID)
,
enabling implementation of a battery removal function if an external pack resistor ID is connected between
ANLG1 and ground.
ANLG1 and ground.
The ANLG1 pin may be used to monitor other parameters than a pack ID resistor. When ANLG1 pin is used as a
generic ADC analog input V(ANLG1) should never exceed V(OUT) – V
generic ADC analog input V(ANLG1) should never exceed V(OUT) – V
(NOBATID)
, to avoid undesired battery
discharge caused by activation of the battery pin discharge circuit.
Copyright © 2006–2008, Texas Instruments Incorporated
73
Product Folder Link(s):