Texas Instruments TXS4558 Evaluation Module TXS4558EVM TXS4558EVM 데이터 시트
제품 코드
TXS4558EVM
PCB Layout
4.2
Jumper Settings
To enable both LDOs at the 2.95V setting
J3 is EN2. A jumper should be placed connecting the center and left pin. This connects EN2 to VCC and
enables VSIM2.
enables VSIM2.
J1 is EN1. A jumper should be placed connecting the center and left pin. This connects EN2 to VCC and
enables VSIM2.
enables VSIM2.
J2 is VSEL1. A jumper should be placed connecting the center and left pin. This connects VSEL1 to VCC
and sets the LDO to output 2.95V.
and sets the LDO to output 2.95V.
J4 is VSEL2. A jumper should be placed connecting the center and left pin. This connects VSEL2 to VCC
and sets the LDO to output 2.95V.
and sets the LDO to output 2.95V.
These settings can be changes according to LDO requirements.
4.3
General Settings
When connecting signals, minimize connection length and keep GND leads short when probing. This will
ensure minimal capacitive, resistive and inductive loading caused by the connection and connectors. For
more information about the device please see the TXS4558 datasheet, or TI
ensure minimal capacitive, resistive and inductive loading caused by the connection and connectors. For
more information about the device please see the TXS4558 datasheet, or TI
’
s support forum
5
PCB Layout
Figure 1. Top Layer
2
TXS4558 Evaluation Module
SLLU153
–
September 2011
Copyright
©
2011, Texas Instruments Incorporated