Texas Instruments TPS23751 Evaluation Module TPS23751EVM-104 TPS23751EVM-104 데이터 시트
제품 코드
TPS23751EVM-104
SLVSB97C – JULY 2012 – REVISED JANUARY 2014
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, 40 V
≤ V
DD
≤ 57 V; V
CTL
= V
MODE
= V
SLPb
= V
B
; V
SRT
= 0.5 V; V
APD
= V
CS
= V
ARTN
=
V
RTN
; CLS, GATE, LED, SRD, T2P open; R
WAKE
= 392 k
Ω; R
DEN
= 24.9 k
Ω; R
T
= 34 k
Ω; C
VB
= C
VC
= 0.1 µF;
–40
≤ T
J
≤ 125°C. Typical values are at 25°C. All voltages referred to V
SS
.
CONTROLLER SECTION
V
C
= 12 V, V
DEN
= V
VSS
, V
ARTN
= V
RTN
= V
SS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
C
(GATE DRIVE SUPPLY)
Output voltage; TPS23752 only
V
VDD
= 48 V, Sleep mode
12
12.8
13.8
V
V
VDD
= 48 V, V
C
= 0 V
1.1
1.5
2.1
I
VC_ST
Startup source current
mA
V
VDD
= 10.9 V, V
C
= 8.6 V
0.9
1.3
1.8
I
VC_OP
Operating current
V
VC
= 12 V, V
CTL
= V
B
0.9
1.8
3.0
mA
t
ST
Bootstrap start up time, C
VC
= 22 µF
V
VDD
= 48 V, measure time from V
VC
(0)
→ V
CUV
103
155
203
ms
V
CUV
V
VC
rising until V
SRD
↓
8.6
8.9
9.2
UVLO threshold
V
V
CUVH
Hysteresis
3
3.2
3.4
V
B
(BIAS SUPPLY)
Output voltage
7.5 V
≤ V
VC
≤ 18 V, 0 ≤ I
VB
≤ 5 mA
4.75
5.00
5.25
V
APD (AUXILIARY POWER DETECT)
V
APDEN
V
APD
↑, measure with respect to ARTN
1.43
1.50
1.57
APD threshold voltage
V
V
APDH
Hysteresis
0.28
0.30
0.32
Leakage current
V
APD
= 18 V
10
µA
RT (OSCILLATOR)
F
SW
Switching frequency in PWM mode
R
T
= 34.0 k
Ω. Measure at GATE
226
251
276
kHz
F
VFO
Switching frequency in VFO mode
V
CTL
= 1.75 V, R
T
= 34.0 k
Ω. Measure at GATE
105
135
165
kHz
D
MAX
Maximum duty cycle
V
CTL
= V
B
, Measure at GATE
75%
80%
85%
CTL (CONTROL – PWM INPUT)
V
CTL
↓ until V
SRD
↑
1.90
2.00
2.10
V
V
SRT
= 0.5V
Hysteresis
(1)
35
mV
V
CTL_VFO
V
CTL
at PWM/VFO transition point
V
CTL
↓ until V
SRD
↑
2.15
2.25
2.35
V
V
SRT
= 1.0 V
Hysteresis
(1)
40.50
mV
T
SSD
Internal soft start delay time
V
CTL
= 3.5 V, measure from switching start to V
CSMAX
1.87
3.01
5.09
ms
Input resistance
70
105
145
k
Ω
V
ZF
Zero frequency threshold (ZF)
V
CTL
↓ until GATE stops switching
1.40
1.50
1.60
V
V
ZDC
Zero duty cycle (ZDC) threshold (VFO disabled)
V
SRT
= V
ARTN
, V
CTL
↓ until GATE stops switching
1.55
1.75
1.95
V
Gain, V
CS
to V
CTL
(1)
5.0
V/V
CS (CURRENT SENSE)
V
CSMAX
Maximum threshold voltage
V
CS
↑ until V
GATE
↓
0.22
0.25
0.28
V
1.60V
≤ V
CTL
≤ 1.90V, V
SRT
= 0.5 V, V
CS
↑ until V
GATE
↓
40
50
60
mV
V
CS_VFO
Peak V
CS
in VFO mode
1.85V
≤ V
CTL
≤ 2.15V, V
SRT
= 1.0 V, V
CS
↑ until V
GATE
↓
85
100
115
mV
V
PK
Internal slope compensation voltage, see
D = D
MAX
32
40
50
mV
I
CS_RAMP
Ramp component of I
CS
D = D
MAX
12
16
25
µA
I
CSDC
DC component of I
CS
1
2
3
µA
Slope compensation ramp start relative to switching
D
SLOPE_ST
30%
34%
39%
period. Refer to
t
1
Turn off delay
V
CS
= 0.3 V, measure t
prf50–50
, see
50
90
ns
t
BLNK
Blanking period
100
150
200
ns
Off state pull-down resistance
290
500
Ω
(1)
Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.
4
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