Texas Instruments BQ24765 Evaluation Module for SMBus Controlled Battery Charger with Integrated FETs BQ24765EVM BQ24765EVM 데이터 시트
제품 코드
BQ24765EVM
www.ti.com
SLUS999 – NOVEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
7.0 V
≤
V(DCINA)
≤
24 V, 0°C < T
J
< +125°C, typical values are at T
A
= 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE UNDERCURRENT COMPARATOR (Cycle-by-Cycle Synchronous to Non-Synchronous)
Cycle-by-cycle Synchronous to
Cycle-by-cycle, (CSOP-CSON) voltage, falling,
V
UCP
Non-Synchronous Transition
LGATE turns-off and latches off until next cycle
5
10
15
mV
Threshold
LOGIC INPUT PIN CHARACTERISTICS (CE, SDA, SCL)
V
IN_LO
Input low threshold voltage
0.8
V
Pull-up CE with
≥
2k
Ω
resistor, or connect directly to
V
IN_HI
Input high threshold voltage
2.1
V
VREF.
V
BIAS
Input bias current
V = 0 to 7V
1
μ
A
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACOK, ICOUT)
V
OUT_LO
Output low saturation voltage
Sink Current = 5 mA
0.5
V
VDDSMB INPUT SUPPLY FOR SMBUS
V
VDDSMB_RANGE
VDDSMB input voltage range
2.7
5.5
V
V
VDDSMB_UVLO_
VDDSMB undervoltage lockout
V
VDDSMB
Rising
2.4
2.5
2.6
V
Threshold_Rising
threshold voltage, rising
V
VDDSMB_UVLO_
VDDSMB undervoltage lockout
V
VDDSMB
Falling
100
150
200
mV
Hyst_Rising
hysteresis voltage, falling
I
VDDSMB_Iq
VDDSMB quiescent current
V
VDDSMB
= SCL = SDA = 3.3 V
20
30
μ
A
SMB TIMING SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
R
SCLK/SDATA rise time
1
µs
t
F
SCLK/SDATA fall time
300
ns
t
W(H)
SCLK pulse width high
4
50
µs
t
W(L)
SCLK Pulse Width Low
4.7
µs
t
SU(STA)
Setup time for START condition
4.7
µs
START condition hold time after which first
t
H(STA)
4
µs
clock pulse is generated
t
SU(DAT)
Data setup time
250
ns
t
H(DAT)
Data hold time
300
ns
t
SU(STOP)
Setup time for STOP condition
4
µs
Bus free time between START and STOP
t
(BUF)
4.7
µs
condition
F
S(CL)
Clock Frequency
10
100
kHz
HOST COMMUNICATION FAILURE
t
timeout
SMBus bus release timeout
22
25
35
ms
t
BOOT
Deglitch for watchdog reset signal
10
ms
t
WDI
Watchdog timeout period
140
170
200
s
OUTPUT BUFFER CHARACTERISTICS
V
(SDAL)
Output LO voltage at SDA, I
(SDA)
= 3 mA
0.4
V
Copyright © 2009, Texas Instruments Incorporated
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