Texas Instruments TPS73601DRBEVM-518 Evaluation Module TPS73601DRBEVM-518 TPS73601DRBEVM-518 데이터 시트
제품 코드
TPS73601DRBEVM-518
T = T + P
J
A
D
JA
´ q
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Operation
2.1.4
J4: GND
This point is the return connection for the output.
2.1.5
JP1: ENABLE
This jumper is used to enable or disable the output of the TPS73x01DRB. Placing a shorting jumper
between pins 1 and 2 (ON position) enables the TPS73x01DRB. Placing the shorting jumper between pins
2 and 3 (OFF position) disables the TPS73x01DRB.
between pins 1 and 2 (ON position) enables the TPS73x01DRB. Placing the shorting jumper between pins
2 and 3 (OFF position) disables the TPS73x01DRB.
2.1.6
JP2: V
OUT
Selection
This jumper sets the desired output voltage from the TPS73x01DRB. Placing a shorting jumper between
the appropriate pins gives the corresponding outputs.
the appropriate pins gives the corresponding outputs.
WARNING
1. The Jumper JP2 should only be changed from one place to
another when the power is off.
2. The user should not touch the jumper JP2 while the power is
applied to the EVM since the output voltage may change due to
the noise pick-up in the feedback path.
the noise pick-up in the feedback path.
3
Operation
This section provides information about the operation of the TPS73x01DRBEVM.
3.1
Configuration and Initial Operation
Connect the positive input power supply to J1. Connect the input power return (ground) to J2. The
TPS73x01DRB has an absolute maximum input voltage of 6.0 V. The recommended maximum operating
voltage is 5.5 V. The actual highest input voltage may be less than 5.5 V as a result of thermal conditions.
See the
TPS73x01DRB has an absolute maximum input voltage of 6.0 V. The recommended maximum operating
voltage is 5.5 V. The actual highest input voltage may be less than 5.5 V as a result of thermal conditions.
See the
section of this manual to determine the highest input voltage for
maintaining a safe junction temperature.
Connect the desired load between J3 (positive lead) and J4 (negative or return lead). Configure jumper
JP2 for the desired output voltage.
JP2 for the desired output voltage.
4
Thermal Guidelines
This section presents guidelines for the thermal management of the TPS73x01DRBEVM-518 board.
4.1
Thermal Considerations
Thermal management is a key design component of any power converter, and is especially important
when power dissipation in the LDO is high. To better help you design the TPS73x01DRB family into your
applications, the following formula should be used to approximate the maximum power dissipation (P
when power dissipation in the LDO is high. To better help you design the TPS73x01DRB family into your
applications, the following formula should be used to approximate the maximum power dissipation (P
DMax
)
at a particular ambient temperature:
(1)
where:
•
T
J
is the junction temperature
•
T
A
is the ambient temperature
•
P
D
is the power dissipation in the IC
•
θ
JA
is the thermal resistance from junction to ambient
3
SBVU014 – August 2009
TPS73x01DRBEVM-518
Copyright © 2009, Texas Instruments Incorporated