Texas Instruments Evaluation Module for BQ24140, 1.5A Dual Input Switchmode Charger with USB-OTG Support BQ24140EVM-003 BQ24140EVM-003 데이터 시트
제품 코드
BQ24140EVM-003
Printed-Circuit Board Layout Guideline
Figure 4. Test Setup for USB OTG Boost Mode
4. Turn on PS #1 output.
5. Software setup: Change Operation Mode to Boost mode.
Measure on VM #2
→
V(J6/TP2, J9/TP13(VBUS, GND)) = 5 V ± 0.2 V
6. Enable Load #1.
Measure on VM #2
→
V(J6/TP2, J9/TP13(VBUS, GND)) = 5 V ± 0.2 V
Measure on CM #1
→
Iin = 330 mA ± 40 mA
Measure on CM #2
→
Io = 200 mA ± 20 mA
7. Turn off PS #1, turn off Load #1, and disconnect.
3
Printed-Circuit Board Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from input to PGND, must be
placed as close as possible to the integrated circuit (IC).
2. The output inductor must be placed close to the IC and the output capacitor connected between the
inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high-frequency oscillation problems, proper
layout to minimize high-frequency current path loop is critical.
through the LC filter and back to the PGND pin. To prevent high-frequency oscillation problems, proper
layout to minimize high-frequency current path loop is critical.
3. The sense resistor must be adjacent to the junction of the inductor and output capacitor. Route the
sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
on top of each other on adjacent layers (do not route the sense leads through a high-current path).
on top of each other on adjacent layers (do not route the sense leads through a high-current path).
4. Place all decoupling capacitors close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals must be routed
away from the high-current paths.
away from the high-current paths.
5. The PCB must have a ground plane (return) connected directly to the return of all components through
vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
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SLUU495A – October 2011 – Revised September 2012 bq24140, Fully Integrated, Dual-Input, Switch-Mode, One-Cell, Li-Ion Charger
With Full USB Compliance and USB-OTG Support EVM
Copyright © 2011–2012, Texas Instruments Incorporated