Texas Instruments CDCE949Perf-EVM - CDCE949 Performance Evaluation Module CDCE949PERF-EVM CDCE949PERF-EVM 데이터 시트
제품 코드
CDCE949PERF-EVM
EEPROM
Xin
Xout
V
DD
GND
V
DDOUT
X-tal
Y2 = 27 MHz
Y1 = 27MHz
Y3 = 27 MHz
LV
CMOS
Pdiv1 =1
Y4 = 27 MHz
Y5 = 27 MHz
Y6 = 27 MHz
Y7 = 27 MHz
Y8 = 27 MHz
Y9 = 27 MHz
LV
CMOS
Pdiv9 = 1
Pdiv8 = 1
M
8
M
9
LV
CMOS
LV
CMOS
Pdiv7 = 1
Pdiv6 = 1
M
6
M
7
LV
CMOS
LV
CMOS
Pdiv5 = 1
Pdiv4 = 1
M
4
M
5
LV
CMOS
LV
CMOS
Pdiv3 = 1
Pdiv2 = 1
M
2
M
3
LV
CMOS
Programming
and
SDA/SCL
Register
Input Clock
M
1
PLL Bypass
PLL 1
power down
M
U
X
1
PLL Bypass
PLL 2
power down
M
U
X
2
PLL Bypass
PLL 3
power down
M
U
X
3
PLL Bypass
PLL 4
power down
M
U
X
4
S0
SDA
SCL
27 MHz
Crystal
Programming Bus
“1” = outputs enabled
“0” = outputs 3-State
SCAS844D – AUGUST 2007 – REVISED MARCH 2010
www.ti.com
Table 3. Y1 Setting
(1)
Y1 SELECTION
Y1
FUNCTION
0
State 0
1
State 1
(1)
State0 and State1 are user-definable in Generic Configuration
Register and can be power down, 3-state, low or active.
Register and can be power down, 3-state, low or active.
The S1/SDA and S2/SCL pins of the CDCE949/CDCEL949 are dual-function pins. In the default configuration
they are defined as SDA/SCL for the serial interface. They can be programmed as control pins (S1/S2) by setting
the appropriate bits in the EEPROM. Note that changes to the Control register (Bit [6] of Byte 02) have no effect
until they are written into the EEPROM.
they are defined as SDA/SCL for the serial interface. They can be programmed as control pins (S1/S2) by setting
the appropriate bits in the EEPROM. Note that changes to the Control register (Bit [6] of Byte 02) have no effect
until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if V
DDOUT
is
forced to GND, the two control-pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE949/CDCEL949 is preconfigured as shown in
. (The input frequency is
passed through to the output as a default.) This allows the device to operate in default mode without the extra
production step of programming it. The default setting appears after power is supplied or after a power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL Interface.
production step of programming it. The default setting appears after power is supplied or after a power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL Interface.
Figure 6. Default Configuration
shows the default setting for the Control Terminal Register (external control pins). In normal operation, all
8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be
selected with S0, as S1 and S2 are configured as programming pins in default mode.
selected with S0, as S1 and S2 are configured as programming pins in default mode.
10
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