Texas Instruments CDCE949Perf-EVM - CDCE949 Performance Evaluation Module CDCE949PERF-EVM CDCE949PERF-EVM 데이터 시트
제품 코드
CDCE949PERF-EVM
SCAS844D – AUGUST 2007 – REVISED MARCH 2010
www.ti.com
DEVICE CHARACTERISTICS (Continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
(1)
MAX
UNIT
CDCE949 – LVCMOS PARAMETER FOR V
DDOUT
= 3.3 V – MODE
V
DDOUT
= 3 V, I
OH
= –0.1 mA
2.9
V
OH
LVCMOS high-level output voltage
V
DDOUT
= 3 V, I
OH
= –8 mA
2.4
V
V
DDOUT
= 3 V, I
OH
= –12 mA
2.2
V
DDOUT
= 3 V, I
OL
= 0.1 mA
0.1
V
OL
LVCMOS low-level output voltage
V
DDOUT
= 3 V, I
OL
= 8 mA
0.5
V
V
DDOUT
= 3 V, I
OL
= 12 mA
0.8
t
PLH
,
Propagation delay
PLL bypass
3.2
ns
t
PHL
t
r
/t
f
Rise and fall time
V
DDOUT
= 3.3 V (20%–80%)
0.6
ns
1 PLL switching, Y2-to-Y3
60
90
t
jit(cc)
Cycle-to-cycle jitter
(2) (3)
ps
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
t
jit(per)
Peak-to-peak period jitter
(2) (3)
ps
4 PLLs switching, Y2-to-Y9
130
180
f
OUT
= 50 MHz; Y1-to-Y3
60
t
sk(o)
Output skew
(4)
ps
f
OUT
= 50 MHz; Y2-to-Y5 or Y6-to-Y9
160
odc
Output duty cycle
(5)
f
VCO
= 100 MHz; Pdiv = 1
45
55
%
CDCE949 – LVCMOS PARAMETER FOR V
DDOUT
= 2.5 V – MODE
V
DDOUT
= 2.3 V, I
OH
= –0.1 mA
2.2
V
OH
LVCMOS high-level output voltage
V
DDOUT
= 2.3 V, I
OH
= –6 mA
1.7
V
V
DDOUT
= 2.3 V, I
OH
= –10 mA
1.6
V
DDOUT
= 2.3 V, I
OL
= 0.1 mA
0.1
V
OL
LVCMOS low-level output voltage
V
DDOUT
= 2.3 V, I
OL
= 6 mA
0.5
V
V
DDOUT
= 2.3 V, I
OL
= 10 mA
0.7
t
PLH
,
Propagation delay
PLL bypass
3.4
ns
t
PHL
t
r
/t
f
Rise and fall time
V
DDOUT
= 2.5 V (20%–80%)
0.8
ns
1 PLL switching, Y2-to-Y3
60
90
ps
t
jit(cc)
Cycle-to-cycle jitter
(2) (3)
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
ps
t
jit(per)
Peak-to-peak period jitter
(2) (3)
4 PLLs switching, Y2-to-Y9
130
180
f
OUT
= 50 MHz; Y1-to-Y3
60
t
sk(o)
Output skew
(4)
ps
f
OUT
= 50 MHz; Y2-to-Y5 or Y6-to-Y9
160
odc
Output duty cycle
(5)
f
VCO
= 100 MHz; Pdiv = 1
45
55
%
(1)
All typical values are at respective nominal V
DD
.
(2)
10000 cycles.
(3)
Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: f
IN
= 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: f
IN
= 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
(4)
The t
sk(o)
specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data
sampled on rising edge (t
r
).
(5)
odc depends on output rise- and fall-time (t
r
/t
f
).
6
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s):