Texas Instruments TPS92551EVM Evaluation Module TPS92551EVM/NOPB TPS92551EVM/NOPB 데이터 시트
제품 코드
TPS92551EVM/NOPB
0
10
20
30
40
50
60
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
I L
ED
(A
)
VIN(V)
1LED
9LED
16LED
3
4
5
6
2
7
EP
V
IN
I
LED
TPS92551
EP
H
ig
h
Po
w
e
r
L
ED
St
ri
n
g
C
IN
C
O
U
T
I
LED2
I
LED1
C
IN
TPS92551
1
3
4
5
6
2
7
1
L
ED+
L
ED+
D
IM
G
N
D
VR
EF
IAD
J
L
ED-
L
ED+
L
ED+
D
IM
G
N
D
VR
EF
IAD
J
L
ED-
C
O
U
T
SNVS805C – MAY 2012 – REVISED MAY 2013
Figure 34. Parallel Operation Circuit Schematic for I
LED
= 900mA
Figure 35. Parallel Operation Results for I
LED
= 900mA, I
LED
vs V
IN
PC Board Layout Considerations
The overall performance of the LED driver is highly depends on the PCB layout. Poor board layout can disrupt
the performance of the TPS92551 and surrounding circuitry by contributing to EMI, ground bounce and resistive
voltage drop in the traces. These can send erroneous signals to the LED driver resulting in poor regulation and
stability. Good layout can be implemented by following a few simple design rules.
the performance of the TPS92551 and surrounding circuitry by contributing to EMI, ground bounce and resistive
voltage drop in the traces. These can send erroneous signals to the LED driver resulting in poor regulation and
stability. Good layout can be implemented by following a few simple design rules.
1. Place C
IN
as close as possible to the V
IN
pin and GND exposed pad (EP).
2. Place C
OUT
(optional for reduction of LED current ripple and EMI compliance) as close as possible to the
VLED+ pin and VLED- pin.
3. The exposed pad (EP) must connect to the GND pin directly.
EMI Design Considerations
From an EMI reduction standpoint, it is imperative to minimize the di/dt current paths (refer to
Therefore, it is essential to connect an 2.2µF capacitor (C
OUT
) across the LED+ pin and LED- pin. This will
minimize the ripple current so that it can reduce radiated EMI (refer to
and
14
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