Texas Instruments CDCLVP2106EVM - CDCLVP2106 Evaluation Module CDCLVP2106EVM CDCLVP2106EVM 데이터 시트
제품 코드
CDCLVP2106EVM
www.ti.com
Output Clock
5
Output Clock
The CDCLVP2106 generates up to 12 LVPECL outputs. Four outputs are available on the
CDCLVP2106EVM (outputs 0, 5, 6, and 11) through the following SMAs:
CDCLVP2106EVM (outputs 0, 5, 6, and 11) through the following SMAs:
•
J13, J23 for OUT0
•
J17, J27 for OUT5
•
J33, J32 for OUT6
•
J39, J38 for OUT11
The LVPECL outputs are terminated with 150
Ω
to ground and ac-coupled to the respective SMAs.
6
Schematics and Layout
through
show the printed circuit board (PCB) schematics.
NOTE:
Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing CDCLVP2106EVM PCBs.
Figure 2. CDCLVP2106EVM—Schematic
3
SCAU037 – August 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Copyright © 2009, Texas Instruments Incorporated