Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 1.9 GHz VCO LMK04803BEVAL/NOPB LMK04803BEVAL/NOPB 데이터 시트

제품 코드

LMK04803BEVAL/NOPB

November 2013

LMK040xx Evaluation Board User’s Guide

SNAU045A

www.ti.com

Connector Name Input/Output Description

Fout

Output

When enabled, buffered VCO output. AC-coupled. The default

configuration on the board contains a 3-dB attenuator on the Fout

signal.

Vcc

Input

DC power supply for the LMK040XX device.

Note: The LMK040XX family contains internal voltage regulators for the

VCO, PLL and related circuitry. The clock outputs do not have an

internal regulator. A clean power supply is required for best

performance.

VccAux

Input

DC power supply for on-board VCXOs, reference oscillators, and

Global Output Enable (GOE).

Notes:

1. Vcc and VccAux power buses may be interconnected by

placing a jumper on the VCC_TP header.

2. VCOs and VCXOs are sensitive to power supply noise. If the

board is configured with and on-board VCXO or on-board

reference clock, best performance will be achieved if a clean

power supply is connected to VccAux.

CLKin0/CLKin0*,

CLKin1/CLKin1*

Input

Reference clock inputs for PLL1. The default board configuration is

setup for a single-ended reference source at CLKin0* (CLKin0 pin is

AC-coupled to ground). The format of the clock input buffer is

programmable in CodeLoader on the

Bits/Pins tab, and may be either

bi-polar junction mode or MOS mode. The input power level for an AC-

coupled differential input should be between -2 dBm and +13 dBm for

bipolar mode and between +4 dBm and +13 dBm for MOS mode. If

either clock input is driven using a single-ended signal, the signal level

should be between -8 dBm and +8 dBm for bipolar mode, and between

-2 dBm and +10 dBm in MOS mode. If a DC-coupled clock is used to

drive either of the inputs, the peak voltage level must be at least 2 volts

and the minimum voltage no greater than 0.4 volts. By default CLKin0 is

the active input in either of the auto-switching modes (CLKin0 non-

revertive, CLKin0 revertive). When loss of CLKin0 is detected, the

device automatically switches to CLKin1 if an active reference clock is

attached. See data sheet for further explanation.

LOS0, LOS1

Output

Loss-of-Signal indicator (CMOS) for CLKin0/0* and CLKin1/1*. See

data sheet for further explanation of the LOS pins.

OSCin/OSCin*

Input

If the evaluation board is not configured with an on-board VCXO

module or on-board crystal-based VCXO, an external VCXO may be

attached to the OSCin/OSCin* SMA connectors. Either a differential or

single-ended device may be used. If a single-end device is used,

OSCin* should be tied to GND through a capacitor that matches the

AC-coupling capacitor value used for the OSCin pin. Pads for this

capacitor are located close to the OSCin* pin. This capacitor is not

placed for either of the default configurations of the board. See the

LMK04000 data sheet for OSCin port signal specifications.

Vtune1

Output

Tuning voltage output from the loop filter for PLL1. This control voltage

should be connected to the voltage control pin if an external VCXO is

used.

Note: Resistor R143 must be populated with a zero ohm resistor to

control an off-board VCXO.

Vtune2

Output

Available to monitor the tuning voltage for the internal VCO. Resistor

R84 must be populated with a zero ohm resistor.

uWire

Input/Output 10-pin header programming interface for the board. CLK, DATA and LE

signal lines. Each of these signals can be monitored through test points

on the board.