Texas Instruments TAS5630PHD Evaluation Module TAS5630PHD2EVM TAS5630PHD2EVM 데이터 시트
제품 코드
TAS5630PHD2EVM
RESET
(SW11)
(SW11)
+50 V
(J15)
LEFT BTL
SPEAKER
OUTPUT
(J11)
RIGHT BTL
SPEAKER
OUTPUT
(J13)
(SW1)
OUTPUT
ST
AGE
CHANNEL
RIGHT
PBL
T
SERight
Input
(J21)
(SW2)
BTL PBTL
BTL PBTL
OUTPUT
ST
AGE
CHANNEL
LEFT
PBTL Mode
Input
Signal
.:
SELeft
Input
(J20)
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Quick Setup Guide
1.2
PCB Key Map
Physical structure for the TAS5630PHD2EVM is illustrated in
Figure 2. Physical Structure for the TAS53630PHDEVM (Approximate Layout)
2
Quick Setup Guide
This chapter describes the TAS5630PHD2EVM board in regards to power supply and system interfaces.
The chapter provides information regarding handling and unpacking, absolute operating conditions, and a
description of the factory default switch and jumper configuration.
The chapter provides information regarding handling and unpacking, absolute operating conditions, and a
description of the factory default switch and jumper configuration.
This section provides a step–by–step guide to configuring the TAS5630PHD2EVM for device evaluation
2.1
Electrostatic Discharge Warning
Many of the components on the TAS5630PHD2EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures may result in damage to EVM
components.
components.
5
SLAU287A – December 2009 – Revised May 2010
TAS5630PHD2EVM
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