Texas Instruments LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00105BEVAL/NOP LMK00105BEVAL/NOPB 데이터 시트
제품 코드
LMK00105BEVAL/NOPB
0.1
P
F
50
:
Trace
CMOS
Driver
Driver
Rs
V
CC
R
B1
R
B2
V
CC
LMK
Input
50
:
V
O,PP
V
O,PP
/2
V
BB
~ (V
O,PP
/2) x 0.5
0.1
P
F
0.1
P
F
50
:
Trace
5
0
:
LMK
Input
0.1
P
F
R
S
CMOS
Driver
SNAS579F – MARCH 2012 – REVISED MAY 2013
APPLICATION INFORMATION
Driving the Clock Inputs
The LMK00105 has a differential input (CLKin/CLKin*) that can accept AC or DC coupled 3.3V/2.5V LVPECL,
LVDS, and other differential and single ended signals that meet the input requirements specified in
LVDS, and other differential and single ended signals that meet the input requirements specified in
. The device can accept a wide range of signals due to its wide input common mode voltage
range (V
CM
) and input voltage swing (V
ID
)/dynamic range. AC coupling may also be employed to shift the input
signal to within the V
CM
range.
To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have a high slew
rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.
For this reason, a differential input signal is recommended over single-ended because it typically provides higher
slew rate and common-mode noise rejection.
rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.
For this reason, a differential input signal is recommended over single-ended because it typically provides higher
slew rate and common-mode noise rejection.
While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it
with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in
the
with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in
the
. For large single-ended input signals, such as 3.3 V or 2.5 V LVCMOS, a 50
Ω
load
resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line
termination to minimize reflections. The CLKin input has an internal bias voltage of about 1.4 V, so the input can
be AC coupled as shown in
termination to minimize reflections. The CLKin input has an internal bias voltage of about 1.4 V, so the input can
be AC coupled as shown in
. The output impedance of the LVCMOS driver plus Rs should be close to
50
Ω
to match the characteristic impedance of the transmission line and load termination.
Figure 8. Preferred Configuration: Single-Ended LVCMOS Input, AC Coupling
A single-ended clock may also be DC coupled to CLKin as shown in
. A 50-
Ω
load resistor should be
placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of
the driver (V
the driver (V
O,PP
/ 2) drives CLKin, CLKin* should be externally biased to the midpoint voltage of the attenuated
input swing ((V
O,PP
/ 2) × 0.5). The external bias voltage should be within the specified input common voltage
(V
CM
) range. This can be achieved using external biasing resistors in the k
Ω
range (R
B1
and R
B2
) or another low-
noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input
slew rate is the highest.
slew rate is the highest.
Figure 9. Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing
10
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