Texas Instruments Evaluation Module for TPS54120 1A Power Supply w/ Integrated DC-DC Converter & Low-Dropout Regulator T TPS54120EVM-103 데이터 시트
제품 코드
TPS54120EVM-103
Board Layout
The input decoupling capacitor of the SW (C5) is located as close as possible to the IC. PVIN and VIN are
connected together in this EVM, and then through vias they are connected to the input voltage trace in the
second internal layer. Whereas, the decoupling capacitor ground is connected through vias to the bottom
layer. The compensation and the soft start capacitors (C6, C7 and C8), the CLK/RT resistor (R3), and the
SW feedback resistor (R6) are grounded to a power ground trace in the center of the top layer. This helps
shield them from noises of the high current ground plane.
connected together in this EVM, and then through vias they are connected to the input voltage trace in the
second internal layer. Whereas, the decoupling capacitor ground is connected through vias to the bottom
layer. The compensation and the soft start capacitors (C6, C7 and C8), the CLK/RT resistor (R3), and the
SW feedback resistor (R6) are grounded to a power ground trace in the center of the top layer. This helps
shield them from noises of the high current ground plane.
The inductor (L1), the boot cap (C12), and the output caps of the SW (C9, C10) are placed on the bottom
layer of the board to shield the switching noise into the LDO side. However, the boot cap (C12) and the
inductor (L1) are connected through vias directly into the PH pin of the IC. This connects them as close as
possible to the PH pin and reduces parasitic inductance of long traces. Also, the noise reduction capacitor
(C13) is placed as close as possible to the IC.
layer of the board to shield the switching noise into the LDO side. However, the boot cap (C12) and the
inductor (L1) are connected through vias directly into the PH pin of the IC. This connects them as close as
possible to the PH pin and reduces parasitic inductance of long traces. Also, the noise reduction capacitor
(C13) is placed as close as possible to the IC.
The input of the LDO is connected to the output of the switcher using a shorting jumper and a long trace
parallel with the trace that connects the ground on the LDO with the ground of the switcher. Critical analog
ground of the LDO circuits such as the voltage set point divider, the LDO input, and output caps are
terminated to ground using a wide ground trace separate from the power ground pour. In addition, the
input and the output LDO capacitors are kept close to the IC. The voltage divider network of the LDO ties
to the LDO output voltage at the copper of the LDO output trace.
parallel with the trace that connects the ground on the LDO with the ground of the switcher. Critical analog
ground of the LDO circuits such as the voltage set point divider, the LDO input, and output caps are
terminated to ground using a wide ground trace separate from the power ground pour. In addition, the
input and the output LDO capacitors are kept close to the IC. The voltage divider network of the LDO ties
to the LDO output voltage at the copper of the LDO output trace.
Figure 9. Top Side Silkscreen and Routing
10
TPS54120EVM, Low Noise 1A Power Supply Evaluation Module
SLVU641
–
January 2012
Copyright
©
2012, Texas Instruments Incorporated