Texas Instruments Evaluation Module for TPS7A7100 Low-Dropout Linear Regulator TPS7A7100EVM-718 TPS7A7100EVM-718 데이터 시트
제품 코드
TPS7A7100EVM-718
Setup
2
Setup
This section describes the connectors and headers on the EVM as well as how to properly connect, set up
and use the TPS7A7x00EVM-718. See the Assembly Layer diagram,
and use the TPS7A7x00EVM-718. See the Assembly Layer diagram,
, for the location and
orientation of referenced components.
2.1
Input/Output Connector-Headers and Jumper Descriptions
•
J1-VIN – Positive (+) input power supply voltage test and measurement header.
•
J2 – VOUT – Output voltage test and measurement header.
•
J3 (pin 1) – VOUT – Regulator output to a high-current load (up to 6 A).
•
J3 (pin 2) – GND – Ground return from the load (up to 6 A)
•
J4 (pin 1) – VIN – Positive (+) input power supply connector.
NOTE:
Twist the positive input lead and ground return lead from the input power supply, and keep
them as short as possible to minimize EMI and source inductance. Additional bulk
capacitance, 68 µF at C5, was added to the EVM to counter source inductances that may
cause ringing on the load transient waveform during high-current transients. This bulk
capacitance is unnecessary in a typical application circuit.
capacitance, 68 µF at C5, was added to the EVM to counter source inductances that may
cause ringing on the load transient waveform during high-current transients. This bulk
capacitance is unnecessary in a typical application circuit.
•
J4 (pin 2) – GND – Negative (–) input power supply return connector. See preceding J4 –VIN (pin 1)
note.
note.
•
J5 - Header for setting the output voltage.
Output Voltage Set: The output voltage is set by jumpering J5 header pins, each assigned to a given
voltage level, to ground where VOUT = Vref + (sum of jumper-voltages). J5 header pins are numbered
sequentially, odd pins (1,3,5, …, 13) ascending leftward of pin 1 on the top row. All odd pins are
connected to ground. Each even pin is numbered right to left sequentially (2,4,6,…,14) on the bottom
row; and each even pin is assigned a unique voltage level. See the pin-to-pin output voltage
assignments in the following table.
voltage level, to ground where VOUT = Vref + (sum of jumper-voltages). J5 header pins are numbered
sequentially, odd pins (1,3,5, …, 13) ascending leftward of pin 1 on the top row. All odd pins are
connected to ground. Each even pin is numbered right to left sequentially (2,4,6,…,14) on the bottom
row; and each even pin is assigned a unique voltage level. See the pin-to-pin output voltage
assignments in the following table.
VOUT = Vref + (Sum of Voltage Levels)
Voltage Level
Voltage Set Pins
Ground Pins
50 mV
2
1
100 mV
4
3
200 mV
6
5
400 mV
8
7
800 mV
10
9
1.6 V
12
11
unused
14
13
Example: Set VOUT to 1.8 V. Connect shorting jumper from pins 10 to 9, 8 to 7, and 4 to 3. VOUT =
Vref + 800 mV + 400 mV + 100 mV = 1.8 V
Vref + 800 mV + 400 mV + 100 mV = 1.8 V
•
J6 – GND – Ground header for test and measurement of VIN.
•
J7 – GND – Ground header for test and measurement of VOUT.
•
JP1 – EN – Enable (Disable) header. Enable the LDO output by shorting EN (pin 2) to ON (pin 1).
Disable the LDO output by shorting EN (pin 2 ) to OFF (pin 3).
Disable the LDO output by shorting EN (pin 2 ) to OFF (pin 3).
•
TP1 – Power Good (PG) test point.
•
TP4 – VIN test point for most accurate measurement of the input voltage characteristics.
•
TP2 – Ground test point to be used with TP4.
•
TP5 – VOUT test point for most accurate measurement of the output voltage.
•
TP3 – Ground test point to be used with TP5.
2
TPS7A7x00EVM-718 Evaluation Module
SLAU430 – February 2012
Copyright © 2012, Texas Instruments Incorporated