Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO LMK04805BEVAL/NOPB LMK04805BEVAL/NOPB 데이터 시트
제품 코드
LMK04805BEVAL/NOPB
L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
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Appendix H: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
1) Confirm Communications
Refer to Appendix G: Properly Configuring LPT Port to troubleshoot this item.
Remember to load device with Ctrl+L.
Remember to load device with Ctrl+L.
2) Confirm PLL1 operation/locking
1) Program LD_MUX = “PLL1_R/2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine CLKin_SEL programming.
ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE.
iii. If not, examine PLL1 register R programming.
iv. If not, examine physical CLKin input.
3) Program LD_MUX = “PLL1_N /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine PLL1 register N programming.
ii. If not, examine physical OSCin input.
Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider
/2, on LD pin should be the same frequency.
5) Program LD_MUX = “PLL1_DLD”
6) Confirm the LD pin output is high.
6) Confirm the LD pin output is high.
i.
If high, then PLL1 is locked, continue to PLL2 operation/locking.
7) If LD pin output is low, but the frequencies are the same, it is possible that excessive
leakage on Vtune pin is causing the digital lock detect to not activate. By default
PLL2 waits for the digital lock detect to go high before allowing PLL2 and the
integrated VCO to lock. Different VCXO models have different input leakage
specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1
charge pump current settings can cause the PLL1 charge pump to operate longer than
the digital lock detect timeout which allows the device to lock, but prevents the
digital lock detect from activating.
PLL2 waits for the digital lock detect to go high before allowing PLL2 and the
integrated VCO to lock. Different VCXO models have different input leakage
specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1
charge pump current settings can cause the PLL1 charge pump to operate longer than
the digital lock detect timeout which allows the device to lock, but prevents the
digital lock detect from activating.
i.
Redesign PLL1 loop filter with higher phase detector frequency
ii.
Redesign PLL1 loop filter with higher charge pump current
iii.
Isolate VCXO tuning input from PLL1 charge pump with an op amp.