Texas Instruments DAC8218EVM - DAC8218 Evaluation Module DAC8218EVM DAC8218EVM 데이터 시트
제품 코드
DAC8218EVM
Power Supplies
The SCLK signal and the CS signal can each be controlled by multiple pins on J2. Pins J2.3 and J2.5
have been shorted together to control SCLK. J2.1, 2.7 and J2.9 have been shorted together to control CS.
have been shorted together to control SCLK. J2.1, 2.7 and J2.9 have been shorted together to control CS.
Pins J2.2, J2.6, J2.8, J2.12, J2.14, J2.15, J2.17, and J2.19 have weak pull-up/-down resistors. These
resistors provide default settings for many of the control pins. These signals can be controlled through the
digital interface or jumpers found directly on the EVM. By default, these signals are pulled high through
10k
resistors provide default settings for many of the control pins. These signals can be controlled through the
digital interface or jumpers found directly on the EVM. By default, these signals are pulled high through
10k
Ω
resistors. J2.1, J2.3, J2.5, J2.7, J2.9, J2.11 are the control line signals for the DAC8218. They are
connected directly to the DAC through 33
Ω
resistors. The J2 header is the only way to access these pins.
See the
for complete details on these pins.
The load DAC (LDAC) pin is connected via jumper JP12 to either the J2.15 pin or the J2.17 pin. Updating
the DAC registers can be completed in two different ways. First, the LDAC pin can be held low; in this
approach, the input registers are immediately updated. Alternatively, the LDAC pin can be held high, and
the DAC registers update when LDAC is taken low. By default, LDAC is pulled high through a 10k
the DAC registers can be completed in two different ways. First, the LDAC pin can be held low; in this
approach, the input registers are immediately updated. Alternatively, the LDAC pin can be held high, and
the DAC registers update when LDAC is taken low. By default, LDAC is pulled high through a 10k
Ω
resistor. A shunt can be placed across jumpers JP14.9 and JP14.10 to connect LDAC to the ground. See
the
the
for more information on updating the DAC.
GPIO signals GPIO0 and GPIO1 can be accessed at JP14 or the J2 header. GPIO2 can only be
accessed at JP14. By default, these signals are each pulled high through a 10k
accessed at JP14. By default, these signals are each pulled high through a 10k
Ω
resistor. However, they
can be tied to ground by vertically applying a shunt across the individual pins on JP14.
4
Power Supplies
Samtec part numbers SSW-105-22-F-D-VS-K and TSM-105-01-T-DV-P provide a 5-pin, dual-row,
header/socket combination at J3.
header/socket combination at J3.
lists the configuration details for J3. The voltage inputs to the
DAC can be applied directly to the device. The DAC8218 requires multiple power supplies to operate.
AV
AV
DD
, AV
SS
, DV
DD
, and IOV
DD
are required to properly power the DAC. The power should be applied in the
order: IOV
DD
, DV
DD
, then AV
DD
and AV
SS
, followed by reference voltage.
CAUTION
This sequence must be followed in order to prevent damage to the device.
Table 4. J3 Configuration: Power-Supply Input
Pin No.
Pin Name
Function
Required
J3.1
+VA
+4.75V to +24V analog
Yes
supply
J3.2
–
VA
-18V to -4.75V analog
Yes
supply
J3.3
+5VA
+5V analog supply
No
J3.4
–
5VA
–
5V analog supply
No
J3.5
DGND
Digital ground input
Yes
J3.6
AGND
Analog ground input
Yes
J3.7
+1.8VD
1.8V digital supply
Optional
J3.8
VD1
Not used
No
J3.9
+3.3VD
3.3V digital supply
Optional
J3.10
+5VD
+5V
Optional
NOTE:
To avoid damage to the DAC8218, DV
DD
must stay greater
than or equal to IOV
DD
.
5
SBAU166A
–
February 2010
–
Revised May 2011
DAC8218EVM
Copyright
©
2010
–
2011, Texas Instruments Incorporated