Texas Instruments DAC8564EVM - DAC8564 Evaluation Module DAC8564EVM DAC8564EVM 데이터 시트
제품 코드
DAC8564EVM
DAC Module
O
u
tp
u
t
B
u
ff
e
r
M
o
d
u
le
VCC
VSS
+3.3VA
VCC
GND
GND
VDD
DAC Out
4 CH
(J3A)
(J3B)
(J3B)
(JMP7)
(JMP17)
External
Reference
Module
VDD
A0/RST
A1/RSTSEL
A1/RSTSEL
SYNC
SCLK
LDAC
TP4
JMP8
TP2
VSS
V
REF
H
V
REF
L
+5VA
DIN
(J4A)
(J4B)
(J4B)
8 CH
EN
A0/
RST
A1/
RSTSEL
TP3
V
REF
H
JMP9
JMP3
JMP4
JMP5
JMP6
JMP10
VSS
(J2A)
(J2B)
(J2B)
(JMP18)
(JMP11)
(JMP12)
(JMP13)
(JMP14)
(JMP12)
(JMP13)
(JMP14)
JMP15
JMP16
+5VA
+3.3VA
+3.3VA
TP7
2
PCB Design and Performance
2.1
PCB Layout
PCB Design and Performance
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The DAC outputs can be monitored through the selected pins of J4A header connector. The outputs can
be switched through each of their respective jumpers, JMP11, JMP12, JMP13, and JMP14 for the
stacking purposes. The stacking of multiple EVMs allows a total of eight (DAC8564/65) DAC channels to
be used provided that the frame synchronization signal, SYNC, is unique for each EVM board stacked.
The SYNC signal can be selected for each EVM board via jumper JMP18.
be switched through each of their respective jumpers, JMP11, JMP12, JMP13, and JMP14 for the
stacking purposes. The stacking of multiple EVMs allows a total of eight (DAC8564/65) DAC channels to
be used provided that the frame synchronization signal, SYNC, is unique for each EVM board stacked.
The SYNC signal can be selected for each EVM board via jumper JMP18.
In addition, the option of selecting the DAC output to be fed to the non-inverting side of the output
operational amplifier, U2, is also possible by using a jumper across the selected pins of J4A. The output
operational amplifier, U2, must be first configured correctly for the desired waveform characteristic (see
section 3 of this user’s guide manual).
operational amplifier, U2, is also possible by using a jumper across the selected pins of J4A. The output
operational amplifier, U2, must be first configured correctly for the desired waveform characteristic (see
section 3 of this user’s guide manual).
A block diagram of the EVM is shown in
Figure 1. DAC8564/65 EVM Block Diagram
This section talks about the layout design of the PCB thereby describing the physical and mechanical
characteristics of the EVM, as well as a brief description of the EVM test performance procedure
performed. The list of components used on this evaluation module is also included in this section.
characteristics of the EVM, as well as a brief description of the EVM test performance procedure
performed. The list of components used on this evaluation module is also included in this section.
The DAC8564/65 EVM is designed to preserve the performance quality of the DAC, device under test, as
specified in the data sheet. Carefully analyzing the EVM’s physical restrictions and the given or known
elements that contributes to the EVM’s performance degradation is the key to a successful design
implementation. These obvious attributes that diminish the performance of the EVM can be easily
addressed during the schematic design phase, by properly selecting the right components and building the
circuit correctly. The circuit must include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components mechanical attributes.
specified in the data sheet. Carefully analyzing the EVM’s physical restrictions and the given or known
elements that contributes to the EVM’s performance degradation is the key to a successful design
implementation. These obvious attributes that diminish the performance of the EVM can be easily
addressed during the schematic design phase, by properly selecting the right components and building the
circuit correctly. The circuit must include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components mechanical attributes.
The obscure part of the design is the layout process in which limited knowledge and inexperience can
easily present a problem. The main concern is primarily with component placement and the proper routing
of signals. The bypass capacitors must be placed as close as possible to the pins, and the analog and
digital signals must be properly separated from each other. The power and ground plane is very important
and must be carefully considered in the layout process. A solid plane is ideally preferred but sometimes
impractical. Therefore, when solid planes are not possible, a split plane does the job as well. When
considering a split plane design, analyze the component placement and carefully split the board into its
analog and digital sections starting from the device under test. The ground plane plays an important role in
controlling the noise and other effects that otherwise contributes to the error of the DAC output. To ensure
that the return currents are handled properly, route the appropriate signals only in their respective
sections, meaning that the analog traces should only lay directly above or below the analog section and
the digital traces in the digital section. Minimize the length of the traces but use the biggest possible trace
width allowable in the design. These design practices discussed can be seen in the following illustrations.
easily present a problem. The main concern is primarily with component placement and the proper routing
of signals. The bypass capacitors must be placed as close as possible to the pins, and the analog and
digital signals must be properly separated from each other. The power and ground plane is very important
and must be carefully considered in the layout process. A solid plane is ideally preferred but sometimes
impractical. Therefore, when solid planes are not possible, a split plane does the job as well. When
considering a split plane design, analyze the component placement and carefully split the board into its
analog and digital sections starting from the device under test. The ground plane plays an important role in
controlling the noise and other effects that otherwise contributes to the error of the DAC output. To ensure
that the return currents are handled properly, route the appropriate signals only in their respective
sections, meaning that the analog traces should only lay directly above or below the analog section and
the digital traces in the digital section. Minimize the length of the traces but use the biggest possible trace
width allowable in the design. These design practices discussed can be seen in the following illustrations.
4
DAC8564/65 Evaluation Module
SLAU252 – June 2008