Texas Instruments TLV71733PEVM-072 Evaluation Module TLV71733PEVM-072 TLV71733PEVM-072 데이터 시트
제품 코드
TLV71733PEVM-072
Thermal Guidelines and Layout Recommendations
Figure 2. Load Step and Transient Response
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Thermal Guidelines and Layout Recommendations
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the low-dropout (LDO) linear regulator is high. Use the following formula to
approximate the maximum power dissipation for the particular ambient temperature:
when the power dissipation in the low-dropout (LDO) linear regulator is high. Use the following formula to
approximate the maximum power dissipation for the particular ambient temperature:
T
J
= T
A
+ P
D
x
θ
JA
Where T
J
is the junction temperature, T
A
is the ambient temperature, P
D
is the power dissipation in the
device (W), and
θ
JA
is the thermal resistance from junction to ambient. All temperatures are in degrees
Celsius. The maximum silicon junction temperature, T
J
, must not be allowed to exceed 150
°
C. The layout
design must use copper trace and plane areas effectively, as thermal sinks, in order not to allow T
J
to
exceed the absolute maximum rating under all temperature conditions and voltage conditions across the
part.
part.
The designer must carefully consider the thermal design of the PCB for optimal performance over
temperature. The actual allowable power dissipation on your PCB is a strong function of your layout.
temperature. The actual allowable power dissipation on your PCB is a strong function of your layout.
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TLV71733PEVM-072 Evaluation Module
SLVU553
–
October 2011
Copyright
©
2011, Texas Instruments Incorporated