Texas Instruments LM5017 Isolated Bias Supply Evaluation Board LM5017ISOEVAL/NOPB LM5017ISOEVAL/NOPB 데이터 시트
제품 코드
LM5017ISOEVAL/NOPB
UVLO
3
RON
4
RTN
1
VIN
2
8
SW
7
BST
6
VCC
5
FB
SO
PowerPAD-
8
PowerPAD-
8
Exp Pad
SW
BST
VCC
FB
8
7
6
5
1
2
3
4
UVLO
RON
RTN
VIN
WSON-8
Exp Pad
SNVS783G – JANUARY 2012 – REVISED DECEMBER 2013
Connection Diagram
Figure 1. Top View (Connect Exposed Pad to RTN)
Figure 2. Top View (Connect Exposed Pad to RTN)
Pin Descriptions
Pin
Name
Description
Application Information
1
RTN
Ground
Ground connection of the integrated circuit.
2
V
IN
Input Voltage
Operating input range is 7.5 V to 100 V.
3
UVLO
Input Pin of Undervoltage Comparator
Resistor divider from V
IN
to UVLO to GND programs the
undervoltage detection threshold. An internal current
source is enabled when UVLO is above 1.225 V to
provide hysteresis. When UVLO pin is pulled below 0.66
V externally, the parts goes in shutdown mode.
source is enabled when UVLO is above 1.225 V to
provide hysteresis. When UVLO pin is pulled below 0.66
V externally, the parts goes in shutdown mode.
4
R
ON
On-Time Control
A resistor between this pin and V
IN
sets the switch on-
time as a function of V
IN
. Minimum recommended on-
time is 100ns at max input voltage.
5
FB
Feedback
This pin is connected to the inverting input of the internal
regulation comparator. The regulation level is 1.225 V.
regulation comparator. The regulation level is 1.225 V.
6
V
CC
Output from the Internal High Voltage Series Pass
The internal V
CC
regulator provides bias supply for the
Regulator. Regulated at 7.6 V
gate drivers and other internal circuitry. A 1.0
μF
decoupling capacitor is recommended.
7
BST
Bootstrap Capacitor
An external capacitor is required between the BST and
SW pins (0.01
SW pins (0.01
μF ceramic). The BST pin capacitor is
charged by the V
CC
regulator through an internal diode
when the SW pin is low.
8
SW
Switching Node
Power switching node. Connect to the output inductor
and bootstrap capacitor.
and bootstrap capacitor.
EP
Exposed Pad
Exposed pad must be connected to RTN pin. Connect to
system ground plane on application board for reduced
thermal resistance.
system ground plane on application board for reduced
thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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