Texas Instruments LMH6522EVAL Evaluation Module LMH6522EVAL/NOPB LMH6522EVAL/NOPB 데이터 시트
제품 코드
LMH6522EVAL/NOPB
INA_P
INA_ N
3
1
1000 pF
6
4
0.01
P
F
CTIA-
CTIA+
GND
GND
TINA
0.01
P
F
CIA-
CIA+
CCTIA
GND
GND
INA-
INA+
INA-
INA+
1
2
2
1
RIAG0+
0.01
P
F
0.01
P
F
0
TC2-1T
3
4
5
2
3
4
5
DVGA
LMH6522
INA+
INA-
2
3
GND
RIAG0-
0
Using with Differential Sources or Loads
Figure 3. Input Schematic
3
Using with Differential Sources or Loads
The LMH6522EVAL board was designed to be easily modified by the customer for fully differential
operation. To modify the board for differential operation it is necessary to remove the transformers and the
resistors that ground the unused signal paths. Next, add coupling capacitors on the IN- and OUT+ signal
lines, and finally place shorting jumpers across the appropriate transformer pads. At this point the
LMH6522EVAL board will be configured for a 100
operation. To modify the board for differential operation it is necessary to remove the transformers and the
resistors that ground the unused signal paths. Next, add coupling capacitors on the IN- and OUT+ signal
lines, and finally place shorting jumpers across the appropriate transformer pads. At this point the
LMH6522EVAL board will be configured for a 100
Ω
differential signal path.
Other load conditions can also be easily matched by placing appropriate components on existing pads on
the evaluation board. When changing components remember to keep the input path AC coupled so that
the input common mode voltage is preserved.
the evaluation board. When changing components remember to keep the input path AC coupled so that
the input common mode voltage is preserved.
4
Gain Control
For ease of use, banks of DIP switches are set up to control gain settings. For high speed interfacing to a
logic analyzer there are also 0.1” header strips. The pin functions for these headers are shown in
logic analyzer there are also 0.1” header strips. The pin functions for these headers are shown in
For detailed instructions on the pin functions, see LMH6522 High Performance Quad DVGA (
The dip switches settings will impact the on-board impedance for the J1 header pins. With the dip
switches should be set to the OPEN position the header pins are unterminated. When the dip switches are
closed the header pins are terminated with 49.9
switches should be set to the OPEN position the header pins are unterminated. When the dip switches are
closed the header pins are terminated with 49.9
Ω
resistors. This would be the preferred setting for most
high speed signal interfaces. For the absolute maximum voltage and current ratings of the digital pins, see
the device-specific data sheet.
the device-specific data sheet.
Table 1. Header Jack Pin Assignments (CONA. CONB, CONC, COND)
(Pin 1 is pin closest to input connectors)
Header Pin
Parallel Function
1
Address bit 0
2
Address bit 1
3
Address bit 2
4
Address bit 3
5
Address bit 4
6
Ground
7
Enable (Tri State Pin)
3
SNOA552B – July 2011 – Revised May 2013
AN-2072 LMH6522 Evaluation Board
Copyright © 2011–2013, Texas Instruments Incorporated