Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE 데이터 시트
제품 코드
TMDSEVM6472LE
PRODUCTPREVIEW
PLLV3
CLKIN3
PLLCTL
PLL3 Controller
DDR2
clock
PLL3
PLLRST
PLLPWRDN
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
7.10 PLL3 and PLL3 Controller
The C6472 device includes a PLL3 and a software-programmable PLL3 controller. The PLL3 controller
generates the clock. The PLL multiply factor is set to x20 for PLL3.
generates the clock. The PLL multiply factor is set to x20 for PLL3.
NOTE
The PLL controller module as described in the TMS320C6472/TMS320TCI648x DSP
Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature
number
Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature
number
) includes a superset of features, some of which are not supported on the
C6472 DSP. The following sections describe the features that are supported; it should be
assumed that any feature not included in these sections is not supported by the C6472 DSP.
assumed that any feature not included in these sections is not supported by the C6472 DSP.
7.10.1 PLL3 Controller Device-Specific Information
7.10.1.1 Internal Clocks and Maximum Operating Frequencies
As shown in
, the PLL3 controller generates only one clock which is used for DDR2.
NOTE
There is a minimum and maximum operating frequency for CLKIN3 and DDR2 clock (the
multiplier is fixed). The clock generator must not be configured to exceed any of these
constraints. For the PLL clocks input and output frequencies, see
multiplier is fixed). The clock generator must not be configured to exceed any of these
constraints. For the PLL clocks input and output frequencies, see
.
Figure 7-34. PLL3 and PLL3 Controller
Table 7-43. PLL3 Clock Frequency Ranges
CLOCK SIGNAL
REQUIRED FREQUENCY
UNIT
CLKIN3
20 - 26.66
MHz
PLLOUT (DDR2 clock)
400 - 533.33
MHz
7.10.1.2 PLL3 Controller
The PLL3 controller provides the control to reset PLL3. It is also capable of placing it in a power-down
condition for systems where DDR2 EMIF is not being used.
condition for systems where DDR2 EMIF is not being used.
7.10.1.3 PLL3 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device powerup. The PLL should not be operated until this stabilization time has
become stable after device powerup. The PLL should not be operated until this stabilization time has
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C64x+ Peripheral Information and Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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