Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the C28x CPU (but not the C28x
DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to
and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation,
clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA
Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC
vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE.
DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to
and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation,
clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA
Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC
vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE.
During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be
remapped to different addresses according to values stored in the EPI Address Map Register in
conjunction with the most significant bit of the incoming address.
remapped to different addresses according to values stored in the EPI Address Map Register in
conjunction with the most significant bit of the incoming address.
The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the
Host Bus Mode (including 8-bit and 16-bit versions).
Host Bus Mode (including 8-bit and 16-bit versions).
7.1.4.1
EPI General-Purpose Mode
The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones
communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower
Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like
ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled
clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose
Mode from the 8-bit and 16-bit Host Bus Modes.
communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower
Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like
ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled
clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose
Mode from the 8-bit and 16-bit Host Bus Modes.
Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The
slave device responding to the bus cycles may use this signal to recognize related words of data and to
speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks,
depending on the clocking mode used.
slave device responding to the bus cycles may use this signal to recognize related words of data and to
speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks,
depending on the clocking mode used.
Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus
cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled
through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach
uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping.
A free-running EPI clock requires another method for determining when data is live, such as the frame pin
or RD/WR strobes.
cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled
through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach
uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping.
A free-running EPI clock requires another method for determining when data is live, such as the frame pin
or RD/WR strobes.
These and numerous other aspects of the General-Purpose Mode are controlled through the General-
Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the
General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.
Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the
General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.
See
for a snapshot of the General-Purpose Mode registers, modes, and features. For more
detailed maps of the General-Purpose Mode, see
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Peripheral Information and Timings
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