Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
BUS
MATRIX
E
P
I
I
C
(2
(2
)
2
S
S
I
(4
)
U
A
R
T
(5
(5
)
U
S
B
+
P
H
Y
(O
T
G
)
E
M
A
C
C
A
N
(2
(2
)
G
P
T
IM
E
R
(4
(4
)
u
C
R
C
W
D
D
O
G
(2
(2
)
N
M
I
W
D
O
G
M3 NMI
NVIC
(NESTED VECTORED INTERRUPT CONTROLLER)
BOOT
ROM
uDMA
RESETS
MPU /
BRIDGE
SECURE
FLASH
(ECC)
FLASHUNCERR
BUSFAULT
BUS CNTRL/FAULT LOGIC
LOCAL MEMORY
M
E
M
O
R
Y
M
N
G
M
T
FLFSM
FLSINGER
A
N
A
LO
G
S
S
U
B
S
Y
S
T
E
M
EXCEPTIONS
FROM M3 CORE
M3NMIINT
M3PORRST
M3HRDFLT
INSTRUCTIONS
D-CODE BUS
M3 SYSTEM BUS
AHB BUS
APB BUS
I-CODE BUS
M3
CPU
M3SYSRST
UART
(5:1)
REQ
(5:1)
REQ
SSI
(3:0)
REQ
(3:0)
REQ
USB
MAC
REQ
MAC
REQ
EPI
REQ
REQ
GPTA/B
(3:0)
(3:0)
REQ
(3:0)
(3:0)
REQ
EMACRX
EMACTX
REQ
EMACTX
REQ
M3DBGRST
M3WDRST
(1:0)
M3NMIRST
M3SWRST
M3NMI
USAGE FAULT
SVCALL
DBG MONITOR
PENDING SV
SYS TICK
SVCALL
DBG MONITOR
PENDING SV
SYS TICK
PROGRAM-
MABLE
PRIORITY
INTERRUPTS
MABLE
PRIORITY
INTERRUPTS
FIXED
PRIORITY
INTERRUPTS
PRIORITY
INTERRUPTS
G
P
IO
_
M
U
X
1
DMA INTRS
DATA
INTERRUPTS
1
2
3
APB BUS (REG ACCESS ONLY)
NVIC
M3NMIINT
ADC
INT
(8:1)
M3NMIINT
E
O
C
IN
T
E
R
R
U
P
T
S
M3 PERIPHERALS
UART
(1:5)
IRQ
(1:5)
IRQ
SSI
(0:3)
IRQ
(0:3)
IRQ
I2C
(1:0)
IRQ
(1:0)
IRQ
CAN0/1
(1:0)
(1:0)
IRQ
(1:0)
(1:0)
IRQ
USB
MAC
IRQ
MAC
IRQ
EPI
IRQ
IRQ
GPTA/B
(3:0)
(3:0)
IRQ
(3:0)
(3:0)
IRQ
GPIO
(S:A)
IRQ
(S:A)
IRQ
WDT
(1:0)
IRQ
(1:0)
IRQ
EMAC
IRQ
IRQ
DMA
SW
IRQ
SW
IRQ
DMA
ERR
IRQ
ERR
IRQ
PERIPHERAL
I/O s
RAMUNCERR
S0-S7
SHARED
RAM
(parity)
MTOC
MSG
RAM
RAM
(parity)
CTOM
MSG
RAM
RAM
(parity)
SHARED RESOURCES
CONTROL SUBSYSTEM
uDMA BUS
CTOM IPC (4:1)
IPC
REGS
FREQ
GASKET
BUS
BRIDGE
C2 - C15
RAM
(parity)
SECURE
C0/C1
RAM
(ECC)
RAMUNCERR
RAMACCVIOL
RAMSINGERR
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
Figure 3-1. Master Subsystem
22
Device Overview
Copyright © 2012–2014, Texas Instruments Incorporated
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