Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.3.6
C28x Serial Peripheral Interface
This device has one C28x SPI. The SPI is a high-speed synchronous serial input/output (I/O) port that
allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller
and external peripherals or another controller. Typical applications include external I/O or peripheral
expansion via devices such as shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit
FIFO for reducing CPU servicing overhead.
allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller
and external peripherals or another controller. Typical applications include external I/O or peripheral
expansion via devices such as shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit
FIFO for reducing CPU servicing overhead.
The SPI module features include:
•
SPISOMI: SPI slave-output/master-input pin
•
SPISIMO: SPI slave-input/master-output pin
•
SPISTE: SPI slave transmit-enable pin
•
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
•
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins.
by the maximum speed of the I/O buffers used on the SPI pins.
•
Data word length: 1 to 16 data bits
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
SPICLK signal and receives data on the rising edge of the SPICLK signal.
–
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
–
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
SPICLK signal and receives data on the falling edge of the SPICLK signal.
–
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
•
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
algorithms.
•
Twelve SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7
When a register is accessed, the register data is in the lower byte (bits 7
−0), and the upper
byte (bits 15
−8) is read as zeros. Writing to the upper byte has no effect.
•
16-level transmit and receive FIFO
•
Delayed transmit control
shows the C28x SPI peripheral.
226
Peripheral Information and Timings
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