Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.8.2
C28x Resets
The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x
Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the
address provided at the top of the Boot ROM Vector Table.
Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the
address provided at the top of the Boot ROM Vector Table.
The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the
M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The
M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated
reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor
in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to
selectively reset the C28x Subsystem from Cortex-M3 software.
M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The
M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated
reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor
in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to
selectively reset the C28x Subsystem from Cortex-M3 software.
The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin
by reading the DEVICECNF register.
by reading the DEVICECNF register.
3.8.3
Analog Subsystem and Shared Resources Resets
Both the Analog Subsystem and the resources shared between the C28x and Cortex-M3 subsystems
(IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog
Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external
ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry.
(IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog
Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external
ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry.
The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a
software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also
output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to
propagate to the Analog Subsystem and the Shared Resources.
software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also
output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to
propagate to the Analog Subsystem and the Shared Resources.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore,
EPI is reset by M3SYSRST.
EPI is reset by M3SYSRST.
3.8.4
Device Boot Sequence
Concerto’s boot sequence is used to configure the Master Subsystem and the Control Subsystem for
execution of application code. The boot sequence involves both internal resources, and resources external
to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-
programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code
(C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four
GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex-
M3 and C28x peripherals for loading the application code into the Master and Control Subsystems.
execution of application code. The boot sequence involves both internal resources, and resources external
to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-
programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code
(C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four
GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex-
M3 and C28x peripherals for loading the application code into the Master and Control Subsystems.
The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by
device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3
NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and
then both bootloaders work in tandem to configure the device, load application code for both processors (if
not already in the Flash), and branch the execution of each processor to a selected location in the
application code.
device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3
NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and
then both bootloaders work in tandem to configure the device, load application code for both processors (if
not already in the Flash), and branch the execution of each processor to a selected location in the
application code.
Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive
state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until
the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level
functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the
Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out
of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the
Control Subsystem, the C-Bootloader enters the C28x processor into the IDLE mode (to wait for the M-
Bootloader to wake up the C28x processor later via the MTOCIPC1 interrupt). Next, the M-Bootloader
reads four GPIO pins (see
state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until
the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level
functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the
Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out
of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the
Control Subsystem, the C-Bootloader enters the C28x processor into the IDLE mode (to wait for the M-
Bootloader to wake up the C28x processor later via the MTOCIPC1 interrupt). Next, the M-Bootloader
reads four GPIO pins (see
) to determine the boot mode for the rest of the M-Bootloader
operation.
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Device Overview
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