Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 데이터 시트
제품 코드
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.11 Master Subsystem Clocking
The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-
down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the
SYSPLLCTL register.
down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the
SYSPLLCTL register.
There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The
10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source
to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the
10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control
Subsystem where this signal can trip the ePWM peripherals.
10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source
to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the
10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control
Subsystem where this signal can trip the ePWM peripherals.
The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources
for the Deep Sleep Clock.
for the Deep Sleep Clock.
There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and
SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has
read access. The C28x can request write access to the above registers through the CLKREQEST register.
Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has
read access. The C28x can request write access to the above registers through the CLKREQEST register.
Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode.
shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and
peripherals.
shows the Cortex-M3 clocks and the Master Subsystem low-power modes.
Table 3-26. Master Subsystem Low-Power Modes
Register Used
Cortex-M3
State of
Clock to
Clock to
to Gate Clocks
Main
USB
Clock to Shared
Low-Power
Cortex-M3
Cortex-M3
Clock to C28x
Analog
to Cortex-M3
PLL
PLL
Resources
Mode
CPU
Peripherals
Subsystem
Peripherals
Run
Active
M3SSCLK
(1)
RCGC
On
On
PLLSYSCLK
(2)
PLLSYSCLK
(2)
ASYSCLK
(3)
RCGC or
Sleep
Stopped
M3SSCLK
(1)
On
On
PLLSYSCLK
(2)
PLLSYSCLK
(2)
ASYSCLK
(3)
SCGC
(4)
RCGC or
Deep Sleep
Stopped
M3DSDIVCLK
(5)
Off
Off
Off
Off
Off
DCGC
(4)
(1)
PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes
10MHZCLK divided-down per the M3SSDIVSEL register.
10MHZCLK divided-down per the M3SSDIVSEL register.
(2)
PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the
PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is
substituted for the PLLSYSCLK.
PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is
substituted for the PLLSYSCLK.
(3)
PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK.
(4)
Depends on the ACG bit of the RCC register.
(5)
32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL
register (source determined inside the DSLPCLKCFG register).
register (source determined inside the DSLPCLKCFG register).
shows the system clock/PLL.
Copyright © 2012–2014, Texas Instruments Incorporated
Device Overview
55
Product Folder Links: