Texas Instruments LX21EVK01 Evaluation Kit LX21EVK01/NOPB LX21EVK01/NOPB 데이터 시트
제품 코드
LX21EVK01/NOPB
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© National Semiconductor Corporation 2009
Printed in U.S.
3
Tx Board Configuration Settings
Component Name
Function
Power Connections
J8
5V DC
Optional 5V DC Power Jack. Note: unpopulated by default
J5
1.8V DC
1.8V VDD Power.
J6 VSS
Ground.
JP12
3.3V DC
3.3V VDD Power (left header pin), Ground (right header pin)
JP11
VDDIO
Input voltage select. Jumper set to 3.3V by default.
Input and Output Connections
J1
44 position wall
header (DIN0 –
header (DIN0 –
DIN20, PCLK)
Connect to data input.
JP1 - JP4
GPO0 - GPO3
Optional general purpose back channel data output
P2
USB Connector
(Type-A Female)
Connect to Channel Link II output (default).
J2 and J3
SMA Connectors
Connect to Channel Link II output. Note: unpopulated by default
Control Connections
S1:1 PDB
Power down mode input.
PDB = H, Serializer is enabled (default)
PDB = L, Serializer is in power-down mode
PDB = H, Serializer is enabled (default)
PDB = L, Serializer is in power-down mode
S1:2 M_S
I2C Mode Select.
M_S = H, Slave Mode – device receives clock and data from local master
M_S = L, Master Mode – device generates and drives the clock line
M_S = H, Slave Mode – device receives clock and data from local master
M_S = L, Master Mode – device generates and drives the clock line
S1:3
RESO
Reserved. Keep set to LOW (default)
JP8 and VR1
CAD
Connect CAD pin to VSS to have the default device PHY address (default setting).
Connect CAD pin to VR1 pin; then adjust VR4 value to select desired device PHY address.
See datasheet for detailed information.
Connect CAD pin to VR1 pin; then adjust VR4 value to select desired device PHY address.
See datasheet for detailed information.
JP9 and J4
I2C Interface
Leave JP8 unconnected if I2C VDD is provided by an external source. (default).
Others
JP6, JP7
Other options
Do not connect