Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 데이터 시트
제품 코드
TMDSADAP180TO100
Z0 = 50
(A)
W
TD = 6 ns
OUTPUT
UNDER
TEST
20 pF
15 W
25 W
D
E
V
IC
E
P
IN
(B
)
DATA SHEET
TIMING
REFERENCE
POINT
TESTER PIN ELECTRONICS
CONCERTO DEVICE
TRANSMISSION LINE
20 pF
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
6.3
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
Letters and symbols and their
meanings:
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
Unknown, changing, or don't care
f
fall time
X
level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
6.3.1
General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.3.2
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
A.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
device pin.
B.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-1. 3.3-V Test Load Circuit
Copyright © 2012–2014, Texas Instruments Incorporated
Electrical Specifications
131
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