Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 데이터 시트
제품 코드
TMDSADAP180TO100
GPIO Signal
1
Sampling Window
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
SYSCLKOUT
(A)
GPxQSELn = 1,0 (6 samples)
(D)
Output From
Qualifier
QUALPRD = 1
(SYSCLKOUT/2)
t
w(IQSW)
t
w(SP)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
(C)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
6.8.2
GPIO - Input Timing
Table 6-33. General-Purpose Input Timing Requirements
MIN
MAX
UNIT
QUALPRD = 0
1t
c(SCO)
cycles
t
w(SP)
Sampling period
QUALPRD
≠ 0
2t
c(SCO)
* QUALPRD
cycles
t
w(IQSW)
Input qualifier sampling window
t
w(SP)
* (n
(1)
– 1)
cycles
Synchronous mode
2t
c(SCO)
cycles
t
w(GPI)
(2)
Pulse duration, GPIO low/high
With input qualifier
t
w(IQSW)
+ t
w(SP)
+ 1t
c(SCO)
cycles
(1)
"n" represents the number of qualification samples as defined by GPxQSELn register.
(2)
For t
w(GPI)
, pulse width is measured from V
IL
to V
IL
for an active low signal and V
IH
to V
IH
for an active high signal.
A.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
B.
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
used.
D.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-6. Sampling Mode
146
Electrical Specifications
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