Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 데이터 시트
제품 코드
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.1.1.2
Start-of-Conversion Triggers
There are eight external SOC triggers that go to each of the two ADC modules (from the Control
Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers
derived from EOC interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1
and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal
SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal
source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field
of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that
channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-to-
digital conversion priority is managed according to the state of the PRICTL register.
Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers
derived from EOC interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1
and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal
SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal
source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field
of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that
channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-to-
digital conversion priority is managed according to the state of the PRICTL register.
7.1.1.3
Analog Inputs
Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group
having a dedicated mux and sample-and-hold unit (see
having a dedicated mux and sample-and-hold unit (see
). Mux A selects one of six possible
analog inputs via AIO MUX. Mux B selects one of seven possible analog inputs—six external inputs via
AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The
Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units
according to the sampling window chosen in the SOCxCTL register for the corresponding channel.
AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The
Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units
according to the sampling window chosen in the SOCxCTL register for the corresponding channel.
7.1.1.4
ADC Result Registers and EOC Interrupts
Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for
ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight
ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts
from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both
the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be
read by a CPU or DMA (see
ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight
ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts
from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both
the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be
read by a CPU or DMA (see
).
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Peripheral Information and Timings
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