Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 데이터 시트
제품 코드
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.2.2.2
Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The
control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first),
parity bit, and the stop bits according to the programmed configuration in the control registers.
control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first),
parity bit, and the stop bits according to the programmed configuration in the control registers.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
has been detected. Overrun, parity, frame error checking, and line-break detection are also performed,
and their status accompanies the data that is written to the receive FIFO.
has been detected. Overrun, parity, frame error checking, and line-break detection are also performed,
and their status accompanies the data that is written to the receive FIFO.
7.2.2.3
Data Transmission and Reception
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four
bits per character for status information. For transmission, data is written into the transmit FIFO. If the
UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH
register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in
the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if
the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated
only when the transmit FIFO is empty, and the last character has been transmitted from the shift register,
including the stop bits. The UART can indicate that it is busy even though the UART may no longer be
enabled.
bits per character for status information. For transmission, data is written into the transmit FIFO. If the
UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH
register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in
the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if
the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated
only when the transmit FIFO is empty, and the last character has been transmitted from the shift register,
including the stop bits. The UART can indicate that it is busy even though the UART may no longer be
enabled.
When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit
has been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL).
has been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is
detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is,
one bit period later), according to the programmed length of the data characters and value of the HSE bit
in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined
in the UARTLCRH register.
clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is
detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is,
one bit period later), according to the programmed length of the data characters and value of the HSE bit
in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined
in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits associated
with that word.
When a full word is received, the data is stored in the receive FIFO along with any error bits associated
with that word.
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Peripheral Information and Timings
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