Texas Instruments LM49370RLEVAL Evaluation Board LM49370RLEVAL/NOPB LM49370RLEVAL/NOPB 데이터 시트
제품 코드
LM49370RLEVAL/NOPB
SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012
Table 3. CLOCKS (0x01h)
Bits
Field
Description
1:0
DAC_CLK
This selects the clock to be used by the audio DAC system.
DAC_CLK
DAC Input Source
00
2
MCLK
01
2
PLL_OUTPUT
10
2
I2S_CLK_IN
11
2
PCM_CLK_IN
7:2
R_DIV
This programs the R divider.
R_DIV
Divide Value
0
Bypass
1
Bypass
2
1.5
3
2
4
2.5
5
3
6
3.5
7
4
8
4.5
9
5
10
5.5
11
6
12
6.5
13 to 61
7 to 31
62
31.5
63
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LM49370 CLOCK NETWORK
The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8
kHz (at point C as marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires
a 12.000MHz (or 12.288MHz) clock (at point B) for 48 kHz data. It is expected that the PLL is used to drive the
audio system operating at 125*fs unless a 12.000 MHz master clock is supplied or the sample rate is always a
multiple of 8 kHz. In this case the PLL can be bypassed to reduce power, with clock division being performed by
the Q and R dividers instead. The PLL can also be bypassed if the system is running at 128*fs and a 12.288MHz
master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I
kHz (at point C as marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires
a 12.000MHz (or 12.288MHz) clock (at point B) for 48 kHz data. It is expected that the PLL is used to drive the
audio system operating at 125*fs unless a 12.000 MHz master clock is supplied or the sample rate is always a
multiple of 8 kHz. In this case the PLL can be bypassed to reduce power, with clock division being performed by
the Q and R dividers instead. The PLL can also be bypassed if the system is running at 128*fs and a 12.288MHz
master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I
2
S clock input as a
source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the
PLL output divided by 2*F
PLL output divided by 2*F
S(DAC)
/F
S(ADC)
or a system clock divided by Q, this allows n*8 kHz recording and 44.1
kHz playback.
MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz.
When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A.
When operating at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A.
This is used to drive the power management and control logic. Performance may not meet the electrical
specifications if the frequency at this point deviates significantly beyond this range.
When operating at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A.
This is used to drive the power management and control logic. Performance may not meet the electrical
specifications if the frequency at this point deviates significantly beyond this range.
Copyright © 2007–2012, Texas Instruments Incorporated
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