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Texas Instruments TAS5721 Evaluation Module TAS5721EVM TAS5721EVM 데이터 시트

제품 코드
TAS5721EVM
다운로드
페이지 중 28
OUTB
OUTD
OUTC
OUT-C
OUT-D
OUTA
HP-INR
HP-INL
HPIR
HPOL
HPOR
HPIL
MCLK
SCLK
LRCLK
SDIN1
SCL
SDA
OUT-A
OUT-B
220ufd/35V
M
C8
+
0.1ufd/50V
0402 X7R
C9
220ufd/35V
M
C31
+
0.1ufd/50V
0402 X7R
C32
0.1ufd/16V
0402 X7R
C19
4.7ufd/6.3V
0402 X5R
C20
1.0in
1.0in
1.0in
1.0in
1.0ufd/10V
0402 X5R
C13
J1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HTSSOP48-DCA
U1
PowerPad
HP-SD
18
0603
R13
330pfd/50V
0402 COG
C27
18
0603
R14
330pfd/50V
0402 COG
C28
18
0603
R15
330pfd/50V
0402 COG
C29
18
0603
R16
330pfd/50V
0402 COG
C30
10ufd/6.3V
0603 X5R
C12
10ufd/6.3V
0603 X5R
C18
DNP
0402
R10
AVDD
AVDD
AVDD
DVDD
15.0K
0402 1/16W
R19
220ufd/35V
M
C43
+
0.33ufd/50V
0805 X7R
C35
15uH/3.5A
A7503AY
L1
15uH/3.5A
A7503AY
L2
JST-VH2
2
1
LEFT
SE-B
1
2
JST-VH2
JST-VH2
2
1
SE-A
15.0K
0402 1/16W
R20
220ufd/35V
M
C44
+
15uH/3.5A
A7503AY
L3
15uH/3.5A
A7503AY
L4
1
2
JST-VH2
RIGHT
0.33ufd/50V
0805 X7R
C36
15.0K
0402 1/16W
R17
220ufd/35V
M
C41
+
15.0K
0402 1/16W
R18
220ufd/35V
M
C42
+
TAS5721EVM_RevA.sbk
JANUARY 19, 2012
RAVINDER SINGH
6529044
A
A
3
LDN
SCH REV
PCB REV
SHEET
DRAWN BY
OF
DATE
FILENAME
TI
PAGE INFO:
DESIGN LEAD
EDGE #
3.5mm
RIGHT
HP-IN
3
1
2
S
h
ie
ld
LEFT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GND
GND
GND
GND
PVDD
PVDD
PVDD
PVDD
PVDD
PVDD
PVDD
GND
C7
0402 X7R
0.033ufd/50V
C1
0402 X5R
1.5ufd/10V
R3
0402
0.0
C2
0402 COG
1000pfd/50V
GND
C3
0402 COG
220pfd/50V
HP-OUT
RIGHT
3.5mm
3
1
2
S
h
ie
ld
LEFT
1.5ufd/10V
0402 X5R
C4
R1
0402
10.0K
10.0K
0402
R4
1000pfd/50V
0402 COG
C5
GND
0.0
0402
R6
10.0K
0402
R2
R5
0402
10.0K
220pfd/50V
0402 COG
C6
GND
C15
0402 X7R
4700pfd/25V
R7
0402
470
C14
0402 X7R
0.047ufd/16V
GND
GND
470
0402
R8
0.047ufd/16V
0402 X7R
C16
4700pfd/25V
0402 X7R
C17
GND
C21
0402 X7R
0.033ufd/50V
0.033ufd/50V
0402 X7R
C22
C34
0402 X7R
0.1ufd/16V
C33
0603 X5R
10ufd/6.3V
GND
GND
DVDD
C26
0402 X7R
0.1ufd/16V
C23
0402 X7R
0.033ufd/50V
C25
0402 X7R
2200pfd/50V
GND
C24
0603 X5R
1.0ufd/25V
GND
C10
0402 X5R
1.0ufd/10V
1.0ufd/10V
0402 X5R
C11
R9
0402
18.20K
NC
NC
HTSSOP48-DCA
U1
TAS5721DCA
14
13
CP
HPVDD
FLTM
GND
15
16
18
17
FLTP
AVDD_REG1
DVDD_REG
GND
23
24
22
21
MCLK
ROSC
ADR
AVDD
19
20
8
7
HPIL
HPOL
HPIR
HPOR
9
10
12
11
HPVSS
CN
5
6
4
3
BSTA
PVDD
OUTA
GND
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDA
SCL
SDIN1
SCLK
LRCLK
NC
TEST
DVDD
GND
GND
PVDD
BSTD
GVDD_REG
AVDD_REG2
SSTIMER
GND
OUTD
OUTC
BSTC
OUTB
BSTB
C37
0805 X7R
0.33ufd/50V
GND
0.33ufd/50V
0805 X7R
C38
GND
C39
0805 X7R
0.33ufd/50V
0.33ufd/50V
0805 X7R
C40
15.0K
0402 1/16W
R12
AVDD
R11
0402 1/16W
15.0K
DVDD
HPOL
FOR PWM
INPUT ONLY
DNP
DNP
DNP
DNP
BOM ONLY
CLICK/POP PERFORMANCE
DEPENDS ON MATCHING
OF C41-C44.  IF THESE
COMPONENTS ARE NOT
WELL MATCHED,
ADDITIONAL BIAS
NETWORK CAN BE
ADDED FOR FURTHER
POP/CLICK REDUCTION.
STUFF OPTION NOTE
STUFF OPTION NOTE
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
STUFF
OPTION
STUFF OPTION
LRCLK
SCLK
SDIN1
SDA
SCL
OUT-D
OUT-C
HPOR
HPOL
HPIL
HPOL
HPIR
HPOR
DVDD_REG1
FLTP
FLTM
AVDD_REG1
AVDD
ADR
MCLK
OUT-B
OUT-A
SC-B
SC-A
SCL
SDA
SDIN1
SCLK
LRCLK
MCLK
SPLIT CAP
SC-B
SC-A
OUT-B
OUT-A
SE
BTL
BTL
SE
BTL = BRIDGE TIED LOAD
SE = SINGLE ENDED
ANALOG
OUTPUTS
TAS5721DCA EVALUATION BOARD
1
MAIN BOARD SCHEMATIC
STANDOFFS
HEADPHONE
OUTPUT
HEADPHONE
INPUT
FROM
MC57xxPSIA
LRCLK
SCLK
SDIN1
SDA
SCL
U1 PINS 5 AND 6
MUST REMAIN FLOATING
Board Layouts, Bill of Materials, and Schematic
6.2
TAS5721-TAS5723EVM Schematic
Figure 7. TAS5721-TAS5723EVM Schematic
13
SLOU346 – July 2012
TAS5721-TAS5723EVM Evaluation Module
Copyright © 2012, Texas Instruments Incorporated