Texas Instruments Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER DAC8531EVM DAC8531EVM 데이터 시트
제품 코드
DAC8531EVM
Stand-Alone DC Mode Test
3-3
EVM Operation
the complete mapping of the respective switches to the data input register for
either DAC8531 or DAC8501. SW3A and SW3B maps out to PD1 (DB13) and
PD0 (DB12) respectively of the DAC data input register (12-bit version).
Figure 3–2 shows it for the 12-bit version (DAC7512/13).
either DAC8531 or DAC8501. SW3A and SW3B maps out to PD1 (DB13) and
PD0 (DB12) respectively of the DAC data input register (12-bit version).
Figure 3–2 shows it for the 12-bit version (DAC7512/13).
Table 3–2. Modes of Operation for the DAC8531
PD1
PD0
Operating Mode
0
0
Normal operation
0
1
Power down mode with output of 1 k
Ω
to GND
1
0
Power down mode with output of 100 k
Ω
to GND
1
1
High-Z
Figure 3–1. Switch SW2 and SW3 Mapping to the Data Input Register (16-Bit Version)
DB23
DB0
X
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
SW2
A
SW2
B
SW2
C
SW2
D
SW3
A
SW3
B
SW3
C
SW3
D
0
0
0
0
0
0
0
0
0
0
CONTROL
BITS
DATA BITS
Since there are only six switches (six MSBs) available to control the data bits,
the maximum value that the data bits can be programmed to is limited to
0xFC00, which does not exactly match the full-scale range of the 16-bit DACs.
This is intended purely for testing purposes and is done to limit the component
count and save space, but still effectively shows that the DAC EVM is properly
functioning.
the maximum value that the data bits can be programmed to is limited to
0xFC00, which does not exactly match the full-scale range of the 16-bit DACs.
This is intended purely for testing purposes and is done to limit the component
count and save space, but still effectively shows that the DAC EVM is properly
functioning.
For the 12-bit version, there are only two bits available to control the data bits
but is sufficient enough to check its functionality.
but is sufficient enough to check its functionality.
Figure 3–2. Switch SW3 Mapping to the Data Input Register (12-Bit Version)
DB23
DB0
X
X
X
X
X
X
D17
D16
D15
D14
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
SW2
A
SW2
B
SW2
C
SW2
D
SW3
A
SW3
B
SW3
C
SW3
D
0
0
0
0
0
0
0
0
0
0
Not used for 12-bit version
CONTROL
BITS
DATA BITS
In general, the 16-bit version and the 12-bit version are identical in operation
with the exception of the number of SCLK periods and the size of their shift and
data registers. With this in mind, this users guide will focus primarily on the
16-bit DAC operation only.
with the exception of the number of SCLK periods and the size of their shift and
data registers. With this in mind, this users guide will focus primarily on the
16-bit DAC operation only.
The self-test mode only provides a 20-MHz SCLK for serial data transfers and
emulates a DSP standard serial interface. The write sequence is initiated by
asserting the SYNC line low and is held low for a period of 25 SCLKs. The serial
data is clocked into the 24-bit shift register, MSB first from the D
emulates a DSP standard serial interface. The write sequence is initiated by
asserting the SYNC line low and is held low for a period of 25 SCLKs. The serial
data is clocked into the 24-bit shift register, MSB first from the D
IN
line, on the
falling edge of SCLK. The last data bit is clocked in on the 24th falling edge (or
16th falling edge for a 12-bit DAC) of SCLK and the DAC is updated. At this
point, the SYNC line is disabled for three SCLK cycles and the write sequence
16th falling edge for a 12-bit DAC) of SCLK and the DAC is updated. At this
point, the SYNC line is disabled for three SCLK cycles and the write sequence