Texas Instruments LV32EVK01 Evaluation Kit LV32EVK01/NOPB LV32EVK01/NOPB 데이터 시트
제품 코드
LV32EVK01/NOPB
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) Board:
The RJ-45 connector P1 provides the interface connection for LVDS signals to the
deserializer board.
The deserializer board is powered externally from the J6 (VDD) and J7 (VSS)
connectors shown below. For the deserializer to be operational, the Power Down
(PWDNB) and Receiver Enable (REN) switches on S1 must be set HIGH. Rising or
falling edge output clock is also selected by S1(R FB): HIGH (rising) or LOW (falling).
The 50 pin IDC Connector J1 provides access to the 32 LVCMOS data and clock
outputs.
deserializer board.
The deserializer board is powered externally from the J6 (VDD) and J7 (VSS)
connectors shown below. For the deserializer to be operational, the Power Down
(PWDNB) and Receiver Enable (REN) switches on S1 must be set HIGH. Rising or
falling edge output clock is also selected by S1(R FB): HIGH (rising) or LOW (falling).
The 50 pin IDC Connector J1 provides access to the 32 LVCMOS data and clock
outputs.
f
J6, J7
c LVDS INPUTS
d LVCMOS OUTPUTS
e FUNCTION CONTROLS
f POWER SUPPLY
g OPTIONAL PARALLEL
LVCMOS LOADING PADS
LVCMOS LOADING PADS
d
J1
e
S1
Note:
V
V
DD
and Gnd MUST be
applied externally here
d
JP3
c
P1 (TOP SIDE)
g
g
g
ASSY DS92LV3242 RX DEMO REV
National Semiconductor Corporation
Date: 9/28/2009
Page 10 of 34
Page 10 of 34