Texas Instruments LV32EVK01 Evaluation Kit LV32EVK01/NOPB LV32EVK01/NOPB 데이터 시트

DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0 

 

 

The 50-pin IDC connector J1 accepts 32 bits of LVCMOS RGB/generic data (TxIN0-
TxIN32) along with the clock input (TCLK).  
 
The SERDES serializer board is powered externally from the J7 (V

DD

) and J8 (V

SS

) 

connectors shown below.  For the serializer to be operational, the Power Down 
(PWDNB) switch on S1 must be set HIGH. The board is factory configured (with series 
0.1

μF capacitors on the LVDS outputs.  Rising or falling edge input clock is also 

selected on S1-TRFB: HIGH (rising) or LOW (falling).  JP2 is configured from the factory 
to be tied to V

DD

 (3.3V), which sets the LVCMOS I/O pins to operate at 3.3V logic levels. 

 
The RJ-45 connector P1 (on the bottom side of the board) provides the interface 
connection to the LVDS signals to the deserializer board.   
 

c

 

LVDS OUTPUTS

  

   

 

f 

J7, J8  

d

 LVCMOS INPUTS 

e 

FUNCTION CONTROLS  

 

f 

POWER SUPPLY

 

g 

50

Ω INPUT 

TERMINATION 

Ω

e

VR1, JP4

J1 

d

 

S1 

e

 

g

 

g

 

g

 

g

 

c

  

P1 (BOTTOM SIDE) 
   (RJ-45) 

National Semiconductor Corporation 

 

Date: 9/28/2009 
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