Texas Instruments AM18x eXperimenter's Kit TMDSEXP1808L TMDSEXP1808L 데이터 시트
제품 코드
TMDSEXP1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.12 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
•
Provides memory protection for fixed and programmable address ranges.
•
Supports multiple programmable address region.
•
Supports secure and debug access privileges.
•
Supports read, write, and execute access privileges.
•
Supports privid(8) associations with ranges.
•
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
•
MMR access is also protected.
Table 6-33. MPU1 Configuration Registers
MPU1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 4000
REVID
Revision ID
0x01E1 4004
CONFIG
Configuration
0x01E1 4010
IRAWSTAT
Interrupt raw status/set
0x01E1 4014
IENSTAT
Interrupt enable status/clear
0x01E1 4018
IENSET
Interrupt enable
0x01E1 401C
IENCLR
Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF
-
Reserved
0x01E1 4200
PROG1_MPSAR
Programmable range 1, start address
0x01E1 4204
PROG1_MPEAR
Programmable range 1, end address
0x01E1 4208
PROG1_MPPA
Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F
-
Reserved
0x01E1 4210
PROG2_MPSAR
Programmable range 2, start address
0x01E1 4214
PROG2_MPEAR
Programmable range 2, end address
0x01E1 4218
PROG2_MPPA
Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F
-
Reserved
0x01E1 4220
PROG3_MPSAR
Programmable range 3, start address
0x01E1 4224
PROG3_MPEAR
Programmable range 3, end address
0x01E1 4228
PROG3_MPPA
Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F
-
Reserved
0x01E1 4230
PROG4_MPSAR
Programmable range 4, start address
0x01E1 4234
PROG4_MPEAR
Programmable range 4, end address
0x01E1 4238
PROG4_MPPA
Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F
-
Reserved
0x01E1 4240
PROG5_MPSAR
Programmable range 5, start address
0x01E1 4244
PROG5_MPEAR
Programmable range 5, end address
0x01E1 4248
PROG5_MPPA
Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F
-
Reserved
0x01E1 4250
PROG6_MPSAR
Programmable range 6, start address
0x01E1 4254
PROG6_MPEAR
Programmable range 6, end address
0x01E1 4258
PROG6_MPPA
Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF
-
Reserved
122
Peripheral Information and Electrical Specifications
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