Texas Instruments AM18x eXperimenter's Kit TMDSEXP1808L TMDSEXP1808L 데이터 시트
제품 코드
TMDSEXP1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
5.5
Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted)
Operating Junction Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DVDD= 3.15V, I
OH
= -4 mA
2.4
V
High-level output voltage
(dual-voltage LVCMOS IOs at 3.3V)
(dual-voltage LVCMOS IOs at 3.3V)
(1)
DVDD= 3.15V, I
OH
= -100
μA
2.95
V
V
OH
High-level output voltage
DVDD= 1.71V, I
OH
= -2 mA
DVDD-0.45
V
(dual-voltage LVCMOS IOs at 1.8V)
(1)
DVDD= 3.15V, I
OL
= 4mA
0.4
V
Low-level output voltage
(dual-voltage LVCMOS I/Os at 3.3V)
(dual-voltage LVCMOS I/Os at 3.3V)
DVDD= 3.15V, I
OL
= 100
μA
0.2
V
V
OL
Low-level output voltage
DVDD= 1.71V, I
OL
= 2mA
0.45
V
(dual-voltage LVCMOS I/Os at 1.8V)
V
I
= VSS to DVDD without opposing
±9
μA
internal resistor
Input current
(1)
V
I
= VSS to DVDD with opposing
70
310
μA
(dual-voltage LVCMOS I/Os)
internal pullup resistor
(3)
I
I
(2)
V
I
= VSS to DVDD with opposing
-75
-270
μA
internal pulldown resistor
(3)
V
I
= VSS to DVDD with opposing
Input current (DDR2/mDDR I/Os)
-77
-286
μA
internal pulldown resistor
(3)
High-level output current
(1)
I
OH
-6
mA
(dual-voltage LVCMOS I/Os)
Low-level output current
(1)
I
OL
6
mA
(dual-voltage LVCMOS I/Os)
Input capacitance (dual-voltage
3
pF
LVCMOS)
Capacitance
Output capacitance (dual-voltage
3
pF
LVCMOS)
(1)
These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are
1.8V IOs and adhere to the JESD79-2A standard. USB0 I/Os adhere to the USB2.0 standard. USB1 I/Os adhere to the USB1.1
standard. SATA I/Os adhere to the SATA-I and SATA-II standards.
1.8V IOs and adhere to the JESD79-2A standard. USB0 I/Os adhere to the USB2.0 standard. USB1 I/Os adhere to the USB1.1
standard. SATA I/Os adhere to the SATA-I and SATA-II standards.
(2)
I
I
applies to input-only pins and bi-directional pins. For input-only pins, I
I
indicates the input leakage current. For bi-directional pins, I
I
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3)
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. The pull-up and pull-down strengths shown represent the
minimum and maximum strength across process variation.
minimum and maximum strength across process variation.
68
Specifications
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