Texas Instruments TPS62120 Evaluation Module TPS62120EVM-640 TPS62120EVM-640 데이터 시트
제품 코드
TPS62120EVM-640
Oscilloscope
Load
DC
Power Supply
+
-
J2
J1
J5
J6
J8
EN
ON
OFF
PG
GND
JP1
JP2
VIN
GND
TPS62120EVM-640
S+
S-
S-
GND
VOUT
J3
J4
J7
S+ S-
Test Configuration
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3.1.10
J8 PG/GND
J8 pin 1 is connected to the Power Good (PG) output of the TPS62120. This open drain output is pulled
up to VOUT with R3. PG output goes high when the FB voltage rises above 95% (typ) of its nominal
value. PG goes low when the FB voltage drops below 90% (typ) of its nominal value.
up to VOUT with R3. PG output goes high when the FB voltage rises above 95% (typ) of its nominal
value. PG goes low when the FB voltage drops below 90% (typ) of its nominal value.
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Test Configuration
4.1
Hardware Setup
illustrates a typical hardware test configuration.
Figure 2. Hardware Board Connection
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TPS62120EVM
SLVU411 – September 2010
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