Texas Instruments Evaluation Module for TPS54528 TPS54528EVM-052 TPS54528EVM-052 데이터 시트
제품 코드
TPS54528EVM-052
t - Time - 400 ns/div
VIN (50 mV/div)
SW (5 V/div)
SLVSAY4C – JULY 2011 – REVISED MARCH 2014
V
O
= 1.05 V
I
O
= 2 A
Figure 17. Voltage Ripple At Input
10 Power Supply Recommendations
The input voltage range is from 4.5V to 18V. The input power supply and the input capacitors should be located
as close to the device as possible to minimize the impedance of the power-supply line.
as close to the device as possible to minimize the impedance of the power-supply line.
11 Layout
11.1 Layout Guidelines
1. The TPS54528 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side
area adjacent to the TPS54528 should be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad of the device using vias as shown. The ground area should be as large as practical.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal of the device.
feedback terminal of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB terminal should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.
Copyright © 2011–2014, Texas Instruments Incorporated
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