Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.7.3.11 ARM/DSP Communications Interrupts
The system module includes registers for generating interrupts between the ARM and DSP.
The DSPINT register shows the status of the ARM-to-DSP interrupts. The DSPINT register format is
shown in
shown in
describes the register bit fields. The ARM may generate an interrupt to
the DSP by setting one of the four INTDSP[3:0] bits or by setting the INTNMI bit in the DSPINTSET
pseudo-register (see
pseudo-register (see
). The interrupt set bit then self-clears and the corresponding
INTDSP[3:0] or INTNMI bit in the DSPINT status register (see
) is automatically set to indicate
that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by writing ‘1’ to
the corresponding bit in the DSPINTCLR register (see
the corresponding bit in the DSPINTCLR register (see
). The ARM may poll the status bit to
determine when the DSP has completed the interrupt service.
The DSP may generate an interrupt to the ARM in the same manner using the ARMINTSET and
ARMINTCLR registers shown/described in
ARMINTCLR registers shown/described in
, and
respectively. The DSP can then view the status of the DSP-to-ARM interrupts via the ARMINT register
shown/described in
shown/described in
and
.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
R-0000 0000 0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
INTNMI
Reserved
INTDSP3
INTDSP2
INTDSP1
INTDSP0
R-0000 000
R-0
R-0000
R-0
R-0
R-0
R-0
LEGEND: R = Read only, n = Value at reset
Figure 4-20. DSPINT Status Register [0x01C4 0060]
Table 4-39. DSPINT Status Register Bit Descriptions
(1)
BIT
NAME
DESCRIPTION
31:9
Reserved
Reserved. A read returns 0.
8
INTNMI
DSP NMI Status
7:4
Reserved
Reserved. A read returns 0.
3
INTDSP3
ARM-to-DSP Int3 Status
2
INTDSP2
ARM-to-DSP Int2 Status
1
INTDSP1
ARM-to-DSP Int1 Status
0
INTDSP0
ARM-to-DSP Int0 Status
(1)
Read only, writes have no effect.
126
Device Configurations
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