Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.5.2
PLL Controller Register Description(s)
A summary of the PLL controller registers is shown in
. For more details, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
Table 7-11. PLL and Reset Controller Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
PLL1 Controller Registers
0x01C4 0800
PID
Peripheral ID Register
0x01C4 08E4
RSTYPE
Reset Type Register
0x01C4 0900
PLLCTL
PLL Controller 1 PLL Control Register
0x01C4 0910
PLLM
PLL Controller 1 PLL Multiplier Control Register
0x01C4 0918
PLLDIV1
PLL Controller 1 Divider 1 Register (SYSCLK1)
0x01C4 091C
PLLDIV2
PLL Controller 1 Divider 2 Register (SYSCLK2)
0x01C4 0920
PLLDIV3
PLL Controller 1 Divider 3 Register (SYSCLK3)
0x01C4 0928
–
Reserved
0x01C4 092C
BPDIV
PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)
0x01C4 0938
PLLCMD
PLL Controller 1 Command Register
0x01C4 093C
PLLSTAT
PLL Controller 1 Status Register (Shows PLLC1 PLLCTL Status)
PLL Controller 1 Clock Align Control Register
0x01C4 0940
ALNCTL
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
PLL Controller 1 PLLDIV Divider Ratio Change Status Register
0x01C4 0944
DCHANGE
(Indicates if SYSCLK Divide Ratio has been modified)
0x01C4 0948
CKEN
PLL Controller 1 Clock Enable Control Register
0x01C4 094C
CKSTAT
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
0x01C4 0950
SYSTAT
PLL Controller 1 SYSCLK Status Register (Indicates SYSCLK on/off Status)
0x01C4 0960
PLLDIV4
PLL Controller 1 Divider 4 Register (SYSCLK4)
0x01C4 0964
PLLDIV5
PLL Controller 1 Divider 5 Register (SYSCLK5)
0x01C4 0968
PLLDIV6
PLL Controller 1 Divider 6 Register (SYSCLK6)
0x01C4 096C
–
Reserved
0x01C4 0970
PLLDIV8
PLL Controller 1 Divider 8 Register (SYSCLK8)
0x01C4 0974
PLLDIV9
PLL Controller 1 Divider 9 Register (SYSCLK9)
PLL2 Controller Registers
0x01C4 0C00
PID
Peripheral ID Register
0x01C4 0D00
PLLCTL
PLL Controller 2 PLL Control Register
0x01C4 0D10
PLLM
PLL Controller 2 PLL Multiplier Control Register
0x01C4 0D18
PLLDIV1
PLL Controller 2 Divider 1 Register (PLL2_SYSCLK1 DDR2 PHY)
0x01C4 0D28
–
Reserved
0x01C4 0D38
PLLCMD
PLL Controller 2 Command Register
0x01C4 0D3C
PLLSTAT
PLL Controller 2 Status Register (Shows PLLC2 PLLCTL Status)
PLL Controller 2 Clock Align Control Register
0x01C4 0D40
ALNCTL
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
PLL Controller 2 PLLDIV Divider Ratio Change Status Register
0x01C4 0D44
DCHANGE
(Indicates if SYSCLK Divide Ratio has been modified)
0x01C4 0D48
CKEN
PLL Controller 2 Clock Enable Control Register
0x01C4 0D4C
CKSTAT
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
0x01C4 0D50
SYSTAT
PLL Controller 2 SYSCLK Status Register (Indicates SYSCLK on/off Status)
0x01C4 0D54 - 0x01C4 0FFF
–
Reserved
156
Peripheral Information and Electrical Specifications
Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s):