Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.18 Host-Port Interface (HPI) Peripheral
The HPI is a parallel port through which a host processor can directly access the CPU memory space.
The host device functions as a master to the interface, which increases ease of access. The host and
CPU can exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the EDMA3
controller.
The host device functions as a master to the interface, which increases ease of access. The host and
CPU can exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the EDMA3
controller.
7.18.1 HPI Device-Specific Information
The DM6467T device includes a user-configurable 32- or 16-bit Host-port interface (HPI32/HPI16).
•
Multiplexed (address/data) operation
•
Configurable single full-word cycle and dual half-word cycle access modes
•
Bursting available utilizing 8-word read and write FIFOs
•
HPIA register supports auto-incrementing
•
HPID register/FIFOs providing data-path between external host interface and system bus
•
Multiple strobes and control signals to allow flexible host connection
•
Configurable asynchronous HRDY output to allow HPI to insert wait states to the Host [System Module
Register HPICTL.HRDYMODE]
Register HPICTL.HRDYMODE]
•
Software control of data prefetching to the HPID/FIFOs
•
DMSoC-to-Host interrupt output signal controlled by HPIC accesses
•
Host-to-DMSoC interrupt controlled by HPIC accesses
NOTE: The DM6467T HPI does not support the HAS feature. For proper HPI operation if the HAS pin
(D4) is routed out, the HAS pin must be pulled up via an external resistor.
(D4) is routed out, the HAS pin must be pulled up via an external resistor.
The DM6467T HPICTL register (0x01C4 0030) is part of the System Module Registers. The HPICTL
register controls write access to the HPI peripheral control and address registers as well as determines
the host time-out value. The HPICTL System Module Register also determines the operation of the HRDY
output which allows the HPI to insert wait states to the Host. For more detailed information on the HPICTL
System Module Register, see
register controls write access to the HPI peripheral control and address registers as well as determines
the host time-out value. The HPICTL System Module Register also determines the operation of the HRDY
output which allows the HPI to insert wait states to the Host. For more detailed information on the HPICTL
System Module Register, see
, Peripheral Selection After Device Reset.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface
(HPI) User's Guide (literature number
(HPI) User's Guide (literature number
7.18.2 HPI Bus Master
The HPI peripheral includes a bus master interface that allows external device initiated transfers to access
the DM6467T system bus.
the DM6467T system bus.
shows the memory map for the HPI master interface.
Table 7-81. HPI Master Memory Map
SIZE
START ADDRESS
END ADDRESS
HPI ACCESS
(BYTES)
0x0000 0000
0x01BF FFFF
28M
Reserved
0x01C0 0000
0x0FFF FFFF
228M
CFG Bus Peripherals
0x1000 0000
0x1000 FFFF
64K
Reserved
0x1001 0000
0x1001 3FFF
16K
ARM RAM 0 (Data)
0x1001 4000
0x1001 7FFF
16K
ARM RAM 1 (Data)
0x1001 8000
0x1001 FFFF
32K
ARM ROM (Data)
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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