Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.20.3 ATA Electrical Data/Timing
All ATA AC timing data described in
–
is provided at the DM6467T
device pins. For more details, see
, Parameter Information.
The AC timing specifications described in
–
assume correct
configuration of the ATA memory-mapped control registers for the selected ATA frequency of operation.
7.20.3.1 ATA PIO Data Transfer AC Timing
Table 7-90. Timings for ATA Module — PIO Data Transfer
(1) (2)
(see
-1G
NO.
UNIT
MODE
MIN
MAX
1
t
0
Cycle time
0-4
(3)
(DATSTB + DATRCVR + 2)P -0.5
ns
2
t
1
Address valid to DIOW/DIOR setup
0-4
(3)
12P - 1.6
ns
3
t
2
DIOW/DIOR pulse duration low
0-4
(3)
(DATSTB + 1)P - 1
ns
0-2
–
ns
4
t
2i
DIOW/DIOR recovery time, pulse duration high
3-4
(3)
(DATRCVR + 1)P - 1
ns
DIOW data setup time, DD[15:0] valid before
5
t
3
0-4
(3)
(DATSTB + 1)P
ns
DIOW rising edge
DIOW data hold time, DD[15:0] valid after DIOW
6
t
4
0-4
(3)
(HWNHLD + 1)P + 1
ns
rising edge
0
50
ns
DIOR data setup time, DD[15:0] valid before DIOR
7
t
5
1
35
ns
rising edge
2-4
(3)
20
ns
DIOR data hold time, DD[15:0] valid after DIOR
8
t
6
0-4
(3)
5
ns
rising edge
Output data 3-state, DD[15:0] 3-state after DIOR
9
t
6Z
0-4
(3)
30
ns
rising edge
10
t
9
DIOW/DIOR to address valid hold
0-4
(3)
(HWNHLD + 1)P - 2.1
ns
Read data setup time, DD[15:0] valid before
11
t
RD
0-4
(3)
0
ns
IORDY active
12
t
A
IORDY setup
0-4
(3) (4)
35
ns
13
t
B
IORDY pulse width
0-4
(3)
1250
ns
14
t
C
IORDY assertion to release
0-4
(3)
5
ns
(1)
P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2)
DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in
the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
).
(3)
The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information,
see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
).
(4)
The t
A
parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order
to meet the t
A
parameter, a minimum frequency for SYSCLK4 is specified for each PIO as follows:
•
PIO mode 0, MIN frequency = 15 MHz
•
PIO mode 1, MIN frequency = 22 MHz
•
PIO mode 2, MIN frequency = 31 MHz
•
PIO mode 3, MIN frequency = 45 MHz
•
PIO mode 4, MIN frequency = 57 MHz
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