Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
GP[x]
Input
GP[x]
Output
4
3
2
1
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.28.3
GPIO Peripheral Input/Output Electrical Data/Timing
Table 7-145. Timing Requirements for GPIO Inputs
(1)
(see
)
-1G
NO.
UNIT
MIN
MAX
1
t
w(GPIH)
Pulse duration, GP[x] input high
2C
(2)
ns
2
t
w(GPIL)
Pulse duration, GP[x] input low
2C
(2)
ns
(1)
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have DM6467T recognize
the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow DM6467T
enough time to access the GPIO register through the internal bus.
the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow DM6467T
enough time to access the GPIO register through the internal bus.
(2)
C = SYSCLK3 period in ns. For example, when running parts at 1 GHz, use C = 4 ns.
Table 7-146. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see
)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
3
t
w(GPOH)
Pulse duration, GP[x] output high
C
(1) (2)
ns
4
t
w(GPOL)
Pulse duration, GP[x] output low
C
(1) (2)
ns
(1)
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
GPIO is dependent upon internal bus activity.
(2)
C = SYSCLK3 period in ns. For example, when running parts at 1 GHz, use C = 4 ns.
Figure 7-94. GPIO Port Timing
344
Peripheral Information and Electrical Specifications
Copyright © 2009–2012, Texas Instruments Incorporated
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